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ArmPkg/ArmMmuLib ARM: assume page tables are in writeback cacheable memory 

Given that these days, our ARM port only supports ARMv7 and later, we
can assume that the page table walker's memory accesses are cache
coherent, and so there is no need to perform cache maintenance. It
does require the page tables themselves to reside in memory mapped as
writeback cacheable so ASSERT() that this is the case.

Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
This commit is contained in:
Ard Biesheuvel 2018-06-21 09:17:52 +02:00
parent 713aea3486
commit 6e275c613e
2 changed files with 3 additions and 13 deletions
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2
ArmPkg/Library/ArmLib/Arm/ArmLibSupport.S
View File

@ -100,8 +100,6 @@ ASM_FUNC(ArmGetTTBR0BaseAddress)
// IN VOID *MVA // R1 // IN VOID *MVA // R1
// ); // );
ASM_FUNC(ArmUpdateTranslationTableEntry) ASM_FUNC(ArmUpdateTranslationTableEntry)
mcr p15,0,R0,c7,c14,1 @ DCCIMVAC Clean data cache by MVA
dsb
mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA mcr p15,0,R1,c8,c7,1 @ TLBIMVA TLB Invalidate MVA
mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp mcr p15,0,R9,c7,c5,6 @ BPIALL Invalidate Branch predictor array. R9 == NoOp
dsb dsb

14
ArmPkg/Library/ArmMmuLib/Arm/ArmMmuLibCore.c
View File

@ -343,17 +343,12 @@ ArmConfigureMmu (
} }
// Translate the Memory Attributes into Translation Table Register Attributes // Translate the Memory Attributes into Translation Table Register Attributes
if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED) || if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_UNCACHED_UNBUFFERED)) {
TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_NON_CACHEABLE : TTBR_NON_CACHEABLE;
} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK) ||
(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) { (TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_BACK)) {
TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC; TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_BACK_ALLOC : TTBR_WRITE_BACK_ALLOC;
} else if ((TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_WRITE_THROUGH) ||
(TranslationTableAttribute == ARM_MEMORY_REGION_ATTRIBUTE_NONSECURE_WRITE_THROUGH)) {
TTBRAttributes = ArmHasMpExtensions () ? TTBR_MP_WRITE_THROUGH : TTBR_WRITE_THROUGH;
} else { } else {
ASSERT (0); // No support has been found for the attributes of the memory region that the translation table belongs to. // Page tables must reside in memory mapped as write-back cacheable
ASSERT (0);
return RETURN_UNSUPPORTED; return RETURN_UNSUPPORTED;
} }
@ -461,9 +456,6 @@ ConvertSectionToPages (
PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor; PageTable[Index] = TT_DESCRIPTOR_PAGE_BASE_ADDRESS(BaseAddress + (Index << 12)) | PageDescriptor;
} }
// Flush d-cache so descriptors make it back to uncached memory for subsequent table walks
WriteBackInvalidateDataCacheRange ((VOID *)PageTable, TT_DESCRIPTOR_PAGE_SIZE);
// Formulate page table entry, Domain=0, NS=0 // Formulate page table entry, Domain=0, NS=0
PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE; PageTableDescriptor = (((UINTN)PageTable) & TT_DESCRIPTOR_SECTION_PAGETABLE_ADDRESS_MASK) | TT_DESCRIPTOR_SECTION_TYPE_PAGE_TABLE;