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SecurityPkg Tcg: Use SW SMI IO port PCD in Tpm.asl

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REF:https://bugzilla.tianocore.org/show_bug.cgi?id=2416

Replaces the hardcoded value of 0xB2 with a PCD for the SMI port access
operation region. This allows platforms to customize the IO port value if
necessary.

Cc: Kun Qin <Kun.Qin@microsoft.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Chao Zhang <chao.b.zhang@intel.com>
Signed-off-by: Michael Kubacki <michael.kubacki@microsoft.com>
Reviewed-by: Guomin Jiang <guomin.jiang@intel.com>
Reviewed-by: Bret Barkelew <bret.barkelew@microsoft.com>
This commit is contained in:
Michael Kubacki 2020-04-07 02:34:22 +08:00 committed by mergify[bot]
parent cda6f9455c
commit 6e3c834ae4
4 changed files with 26 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
SecurityPkg/Tcg/Tcg2Smm/Tcg2Smm.inf
View File

@ -21,6 +21,7 @@
# This external input must be validated carefully to avoid security issue. # This external input must be validated carefully to avoid security issue.
# #
# Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2015 - 2019, Intel Corporation. All rights reserved.<BR>
# Copyright (c) Microsoft Corporation.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
## ##
@ -70,6 +71,9 @@
gEfiSmmVariableProtocolGuid ## CONSUMES gEfiSmmVariableProtocolGuid ## CONSUMES
gEfiAcpiTableProtocolGuid ## CONSUMES gEfiAcpiTableProtocolGuid ## CONSUMES
[FixedPcd]
gEfiSecurityPkgTokenSpaceGuid.PcdSmiCommandIoPort ## CONSUMES
[Pcd] [Pcd]
gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## SOMETIMES_CONSUMES

18
SecurityPkg/Tcg/Tcg2Smm/Tpm.asl
View File

@ -4,7 +4,7 @@
Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR> Copyright (c) 2015 - 2018, Intel Corporation. All rights reserved.<BR>
(c)Copyright 2016 HP Development Company, L.P.<BR> (c)Copyright 2016 HP Development Company, L.P.<BR>
Copyright (c) 2017, Microsoft Corporation. All rights reserved. <BR> Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -41,10 +41,10 @@ DefinitionBlock (
// //
// Operational region for Smi port access // Operational region for Smi port access
// //
OperationRegion (SMIP, SystemIO, 0xB2, 1) OperationRegion (SMIP, SystemIO, FixedPcdGet16 (PcdSmiCommandIoPort), 1)
Field (SMIP, ByteAcc, NoLock, Preserve) Field (SMIP, ByteAcc, NoLock, Preserve)
{ {
IOB2, 8 IOPN, 8
} }
// //
@ -258,7 +258,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (MCIN, IOB2) Store (MCIN, IOPN)
} }
} }
Return (0) Return (0)
@ -359,7 +359,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOPN)
Return (FRET) Return (FRET)
@ -390,7 +390,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOPN)
Store (LPPR, Index (TPM3, 0x01)) Store (LPPR, Index (TPM3, 0x01))
Store (PPRP, Index (TPM3, 0x02)) Store (PPRP, Index (TPM3, 0x02))
@ -422,7 +422,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOPN)
Return (FRET) Return (FRET)
} }
Case (8) Case (8)
@ -436,7 +436,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOPN)
Return (FRET) Return (FRET)
} }
@ -475,7 +475,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (MCIN, IOB2) Store (MCIN, IOPN)
Return (MRET) Return (MRET)
} }
Default {BreakPoint} Default {BreakPoint}

4
SecurityPkg/Tcg/TcgSmm/TcgSmm.inf
View File

@ -10,6 +10,7 @@
# This external input must be validated carefully to avoid security issue. # This external input must be validated carefully to avoid security issue.
# #
# Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
# Copyright (c) Microsoft Corporation.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
## ##
@ -63,6 +64,9 @@
gEfiSmmVariableProtocolGuid ## CONSUMES gEfiSmmVariableProtocolGuid ## CONSUMES
gEfiAcpiTableProtocolGuid ## CONSUMES gEfiAcpiTableProtocolGuid ## CONSUMES
[FixedPcd]
gEfiSecurityPkgTokenSpaceGuid.PcdSmiCommandIoPort ## CONSUMES
[Pcd] [Pcd]
gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES gEfiSecurityPkgTokenSpaceGuid.PcdTpmInstanceGuid ## CONSUMES
gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## SOMETIMES_CONSUMES gEfiMdeModulePkgTokenSpaceGuid.PcdAcpiDefaultOemId ## SOMETIMES_CONSUMES

17
SecurityPkg/Tcg/TcgSmm/Tpm.asl
View File

@ -3,6 +3,7 @@
and MemoryClear. and MemoryClear.
Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR> Copyright (c) 2011 - 2018, Intel Corporation. All rights reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent SPDX-License-Identifier: BSD-2-Clause-Patent
**/ **/
@ -41,10 +42,10 @@ DefinitionBlock (
// //
// Operational region for Smi port access // Operational region for Smi port access
// //
OperationRegion (SMIP, SystemIO, 0xB2, 1) OperationRegion (SMIP, SystemIO, FixedPcdGet16 (PcdSmiCommandIoPort), 1)
Field (SMIP, ByteAcc, NoLock, Preserve) Field (SMIP, ByteAcc, NoLock, Preserve)
{ {
IOB2, 8 IOPN, 8
} }
// //
@ -96,7 +97,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (MCIN, IOB2) Store (MCIN, IOPN)
} }
} }
Return (0) Return (0)
@ -196,7 +197,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOPN)
Return (FRET) Return (FRET)
@ -227,7 +228,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOPN)
Store (LPPR, Index (TPM3, 0x01)) Store (LPPR, Index (TPM3, 0x01))
Store (PPRP, Index (TPM3, 0x02)) Store (PPRP, Index (TPM3, 0x02))
@ -255,7 +256,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOPN)
Return (FRET) Return (FRET)
} }
Case (8) Case (8)
@ -269,7 +270,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (PPIN, IOB2) Store (PPIN, IOPN)
Return (FRET) Return (FRET)
} }
@ -308,7 +309,7 @@ DefinitionBlock (
// //
// Trigger the SMI interrupt // Trigger the SMI interrupt
// //
Store (MCIN, IOB2) Store (MCIN, IOPN)
Return (MRET) Return (MRET)
} }
Default {BreakPoint} Default {BreakPoint}