From 6e52f058f35223b48a3bd9fc1b3bd3530fd730e1 Mon Sep 17 00:00:00 2001 From: Andrei Warkentin Date: Wed, 1 Mar 2023 10:48:17 -0600 Subject: [PATCH] OvmfPkg: RiscVVirt: Add missing SerialPortInitialize to Sec If the SerialPortLib had any initialization needed, this would be skipped in the RiscVVirt Sec. Follow the example seen elsewhere (ArmVirtPkg PrePi). Seen with BaseSerialPortLibRiscVSbiLibRam not using DBCN in Sec, yet using DBCN elsewhere. Cc: Daniel Schaefer Signed-off-by: Andrei Warkentin Reviewed-by: Sunil V L Reviewed-by: Michael D Kinney --- OvmfPkg/RiscVVirt/Sec/SecMain.c | 4 +++- OvmfPkg/RiscVVirt/Sec/SecMain.h | 1 + OvmfPkg/RiscVVirt/Sec/SecMain.inf | 1 + 3 files changed, 5 insertions(+), 1 deletion(-) diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.c b/OvmfPkg/RiscVVirt/Sec/SecMain.c index b052048178..6db39b9401 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.c +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.c @@ -1,7 +1,7 @@ /** @file RISC-V SEC phase module for Qemu Virt. - Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.
+ Copyright (c) 2008 - 2023, Intel Corporation. All rights reserved.
Copyright (c) 2022, Ventana Micro Systems Inc. All rights reserved.
SPDX-License-Identifier: BSD-2-Clause-Patent @@ -57,6 +57,8 @@ SecStartup ( UINT64 StackBase; UINT32 StackSize; + SerialPortInitialize (); + // // Report Status Code to indicate entering SEC core // diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.h b/OvmfPkg/RiscVVirt/Sec/SecMain.h index 83a8058efe..7c7650f0d2 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.h +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.h @@ -29,6 +29,7 @@ #include #include #include +#include #include /** diff --git a/OvmfPkg/RiscVVirt/Sec/SecMain.inf b/OvmfPkg/RiscVVirt/Sec/SecMain.inf index aed35d3af5..0e2a5785e8 100644 --- a/OvmfPkg/RiscVVirt/Sec/SecMain.inf +++ b/OvmfPkg/RiscVVirt/Sec/SecMain.inf @@ -48,6 +48,7 @@ FdtLib MemoryAllocationLib HobLib + SerialPortLib [Ppis] gEfiTemporaryRamSupportPpiGuid # PPI ALWAYS_PRODUCED