tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

ArmPkg: remove cache maintenance by VA operation range size threshold 

This removes the range size threshold for virtual address based cache
maintenance instructions that operate on VA ranges to be 'promoted' to
use set/way instructions.

Doing so is unsafe: set/way operations are fundamentally different
from VA operations, and really only suitable for cleaning or invalidating
a cache when turning it on or off.

To quote the ARM ARM (DDI0487A_d G3.4):
"""
Since the set/way instructions are performed only locally, there is no
guarantee of the atomicity of cache maintenance between different PEs,
even if those different PEs are each performing the same cache maintenance
instructions at the same time. Since any cacheable line can be allocated
into the cache at any time, it is possible for [a] cache line to migrate
from an entry in the cache of one PE to the cache of a different PE in a
manner that the cache line avoids being affected by set/way based cache
maintenance. Therefore, ARM strongly discourages the use of set/way
instructions to manage coherency in coherent systems.
"""

Contributed-under: TianoCore Contribution Agreement 1.0
Reviewed-by: Olivier Martin <Olivier.Martin@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17176 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel 2015-04-14 11:54:40 +00:00 committed by oliviermartin
parent d94a48c71a
commit 6ea34e3a45
15 changed files with 12 additions and 53 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
ArmPkg/ArmPkg.dec
View File

@ -82,8 +82,7 @@
gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002
# This PCD will free the unallocated buffers if their size reach this threshold.
# We set the default value to 512MB.
gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000043
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003
gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005

29
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.c
View File

@ -20,27 +20,20 @@ VOID
CacheRangeOperation (
IN VOID *Start,
IN UINTN Length,
IN CACHE_OPERATION CacheOperation,
IN LINE_OPERATION LineOperation
)
{
UINTN ArmCacheLineLength = ArmDataCacheLineLength();
UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
ArmDrainWriteBuffer ();
CacheOperation ();
} else {
// Align address (rounding down)
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
UINTN EndAddress = (UINTN)Start + Length;
// Align address (rounding down)
UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
UINTN EndAddress = (UINTN)Start + Length;
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
LineOperation(AlignedAddress);
AlignedAddress += ArmCacheLineLength;
}
// Perform the line operation on an address in each cache line
while (AlignedAddress < EndAddress) {
LineOperation(AlignedAddress);
AlignedAddress += ArmCacheLineLength;
}
}
@ -70,7 +63,7 @@ InvalidateInstructionCacheRange (
IN UINTN Length
)
{
CacheRangeOperation (Address, Length, ArmCleanDataCacheToPoU, ArmCleanDataCacheEntryByMVA);
CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA);
ArmInvalidateInstructionCache ();
return Address;
}
@ -91,7 +84,7 @@ WriteBackInvalidateDataCacheRange (
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);
CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA);
return Address;
}
@ -111,7 +104,7 @@ WriteBackDataCacheRange (
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);
CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA);
return Address;
}
@ -122,6 +115,6 @@ InvalidateDataCacheRange (
IN UINTN Length
)
{
CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);
CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA);
return Address;
}

3
ArmPkg/Library/ArmCacheMaintenanceLib/ArmCacheMaintenanceLib.inf
View File

@ -31,6 +31,3 @@
[LibraryClasses]
ArmLib
BaseLib
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

3
ArmPkg/Library/ArmLib/AArch64/AArch64Lib.inf
View File

@ -41,6 +41,3 @@
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

3
ArmPkg/Library/ArmLib/AArch64/AArch64LibPrePi.inf
View File

@ -43,6 +43,3 @@
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

3
ArmPkg/Library/ArmLib/AArch64/AArch64LibSec.inf
View File

@ -38,6 +38,3 @@
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

1
ArmPkg/Library/ArmLib/Arm11/Arm11Lib.inf
View File

@ -47,5 +47,4 @@
gArmTokenSpaceGuid.PcdRelocateVectorTable
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress

1
ArmPkg/Library/ArmLib/Arm11/Arm11LibPrePi.inf
View File

@ -47,5 +47,4 @@
gArmTokenSpaceGuid.PcdRelocateVectorTable
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress

1
ArmPkg/Library/ArmLib/Arm11/Arm11LibSec.inf
View File

@ -43,5 +43,4 @@
gArmTokenSpaceGuid.PcdRelocateVectorTable
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress

3
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLib.inf
View File

@ -41,6 +41,3 @@
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

3
ArmPkg/Library/ArmLib/Arm9/Arm9ArmLibPrePi.inf
View File

@ -41,6 +41,3 @@
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

3
ArmPkg/Library/ArmLib/ArmV7/ArmV7Lib.inf
View File

@ -48,6 +48,3 @@
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

3
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
View File

@ -48,6 +48,3 @@
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

3
ArmPkg/Library/ArmLib/ArmV7/ArmV7LibSec.inf
View File

@ -42,6 +42,3 @@
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold

3
ArmPkg/Library/ArmLib/Null/NullArmLib.inf
View File

@ -40,6 +40,3 @@
[Protocols]
gEfiCpuArchProtocolGuid
[FixedPcd]
gArmTokenSpaceGuid.PcdArmCacheOperationThreshold