mirror of https://github.com/acidanthera/audk.git
ArmPkg: remove cache maintenance by VA operation range size threshold
This removes the range size threshold for virtual address based cache maintenance instructions that operate on VA ranges to be 'promoted' to use set/way instructions. Doing so is unsafe: set/way operations are fundamentally different from VA operations, and really only suitable for cleaning or invalidating a cache when turning it on or off. To quote the ARM ARM (DDI0487A_d G3.4): """ Since the set/way instructions are performed only locally, there is no guarantee of the atomicity of cache maintenance between different PEs, even if those different PEs are each performing the same cache maintenance instructions at the same time. Since any cacheable line can be allocated into the cache at any time, it is possible for [a] cache line to migrate from an entry in the cache of one PE to the cache of a different PE in a manner that the cache line avoids being affected by set/way based cache maintenance. Therefore, ARM strongly discourages the use of set/way instructions to manage coherency in coherent systems. """ Contributed-under: TianoCore Contribution Agreement 1.0 Reviewed-by: Olivier Martin <Olivier.Martin@arm.com> Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17176 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Ard Biesheuvel
oliviermartin
parent
d94a48c71a
commit
6ea34e3a45
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@ -82,8 +82,7 @@
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gArmTokenSpaceGuid.PcdArmUncachedMemoryMask|0x0000000080000000|UINT64|0x00000002
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# This PCD will free the unallocated buffers if their size reach this threshold.
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# We set the default value to 512MB.
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gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000043
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold|1024|UINT32|0x00000003
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gArmTokenSpaceGuid.PcdArmFreeUncachedMemorySizeThreshold|0x20000000|UINT64|0x00000003
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0xffff0000|UINT32|0x00000004
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gArmTokenSpaceGuid.PcdCpuResetAddress|0x00000000|UINT32|0x00000005
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@ -20,18 +20,12 @@ VOID
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CacheRangeOperation (
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IN VOID *Start,
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IN UINTN Length,
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IN CACHE_OPERATION CacheOperation,
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IN LINE_OPERATION LineOperation
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)
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{
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UINTN ArmCacheLineLength = ArmDataCacheLineLength();
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UINTN ArmCacheLineAlignmentMask = ArmCacheLineLength - 1;
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UINTN ArmCacheOperationThreshold = PcdGet32(PcdArmCacheOperationThreshold);
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if ((CacheOperation != NULL) && (Length >= ArmCacheOperationThreshold)) {
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ArmDrainWriteBuffer ();
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CacheOperation ();
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} else {
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// Align address (rounding down)
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UINTN AlignedAddress = (UINTN)Start - ((UINTN)Start & ArmCacheLineAlignmentMask);
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UINTN EndAddress = (UINTN)Start + Length;
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@ -42,7 +36,6 @@ CacheRangeOperation (
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AlignedAddress += ArmCacheLineLength;
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}
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}
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}
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VOID
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EFIAPI
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@ -70,7 +63,7 @@ InvalidateInstructionCacheRange (
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IN UINTN Length
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)
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{
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CacheRangeOperation (Address, Length, ArmCleanDataCacheToPoU, ArmCleanDataCacheEntryByMVA);
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CacheRangeOperation (Address, Length, ArmCleanDataCacheEntryByMVA);
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ArmInvalidateInstructionCache ();
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return Address;
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}
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@ -91,7 +84,7 @@ WriteBackInvalidateDataCacheRange (
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IN UINTN Length
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)
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{
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CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCache, ArmCleanInvalidateDataCacheEntryByMVA);
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CacheRangeOperation(Address, Length, ArmCleanInvalidateDataCacheEntryByMVA);
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return Address;
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}
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@ -111,7 +104,7 @@ WriteBackDataCacheRange (
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IN UINTN Length
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)
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{
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CacheRangeOperation(Address, Length, ArmCleanDataCache, ArmCleanDataCacheEntryByMVA);
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CacheRangeOperation(Address, Length, ArmCleanDataCacheEntryByMVA);
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return Address;
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}
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@ -122,6 +115,6 @@ InvalidateDataCacheRange (
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IN UINTN Length
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)
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{
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CacheRangeOperation(Address, Length, NULL, ArmInvalidateDataCacheEntryByMVA);
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CacheRangeOperation(Address, Length, ArmInvalidateDataCacheEntryByMVA);
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return Address;
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}
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@ -31,6 +31,3 @@
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[LibraryClasses]
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ArmLib
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BaseLib
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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@ -41,6 +41,3 @@
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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@ -43,6 +43,3 @@
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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@ -38,6 +38,3 @@
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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@ -47,5 +47,4 @@
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gArmTokenSpaceGuid.PcdRelocateVectorTable
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
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@ -47,5 +47,4 @@
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gArmTokenSpaceGuid.PcdRelocateVectorTable
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
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@ -43,5 +43,4 @@
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gArmTokenSpaceGuid.PcdRelocateVectorTable
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress
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@ -41,6 +41,3 @@
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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@ -41,6 +41,3 @@
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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@ -48,6 +48,3 @@
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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@ -48,6 +48,3 @@
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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@ -42,6 +42,3 @@
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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@ -40,6 +40,3 @@
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[Protocols]
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gEfiCpuArchProtocolGuid
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[FixedPcd]
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gArmTokenSpaceGuid.PcdArmCacheOperationThreshold
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