mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/RegisterCpuFeaturesLib: Delete CPU_FEATURE_[BEFORE|AFTER]
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1366
Commit b3c71b472d
supported MSR setting
in different scopes. It added below macro:
CPU_FEATURE_THREAD_BEFORE
CPU_FEATURE_THREAD_AFTER
CPU_FEATURE_CORE_BEFORE
CPU_FEATURE_CORE_AFTER
CPU_FEATURE_PACKAGE_BEFORE
CPU_FEATURE_PACKAGE_AFTER
And it re-interpreted CPU_FEATURE_BEFORE as CPU_FEATURE_THREAD_BEFORE
and CPU_FEATURE_AFTER as CPU_FEATURE_THREAD_AFTER.
This patch retires CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER
completely.
Signed-off-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Eric Dong <eric.dong@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
This commit is contained in:
parent
3e63a91b17
commit
707e6be745
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@ -1,7 +1,7 @@
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/** @file
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Register CPU Features Library to register and manage CPU features.
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -69,17 +69,8 @@
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#define CPU_FEATURE_BEFORE_ALL BIT23
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#define CPU_FEATURE_AFTER_ALL BIT24
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//
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// CPU_FEATURE_BEFORE and CPU_FEATURE_AFTER only mean Thread scope
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// before and Thread scope after.
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// It will be replace with CPU_FEATURE_THREAD_BEFORE and
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// CPU_FEATURE_THREAD_AFTER, and should not be used anymore.
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//
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#define CPU_FEATURE_BEFORE BIT25
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#define CPU_FEATURE_AFTER BIT26
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#define CPU_FEATURE_THREAD_BEFORE CPU_FEATURE_BEFORE
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#define CPU_FEATURE_THREAD_AFTER CPU_FEATURE_AFTER
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#define CPU_FEATURE_THREAD_BEFORE BIT25
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#define CPU_FEATURE_THREAD_AFTER BIT26
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#define CPU_FEATURE_CORE_BEFORE BIT27
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#define CPU_FEATURE_CORE_AFTER BIT28
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#define CPU_FEATURE_PACKAGE_BEFORE BIT29
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@ -2,7 +2,7 @@
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This library registers CPU features defined in Intel(R) 64 and IA-32
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Architectures Software Developer's Manual.
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -95,7 +95,7 @@ CpuCommonFeaturesLibConstructor (
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SmxSupport,
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SmxInitialize,
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CPU_FEATURE_SMX,
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CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEFORE,
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CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_THREAD_BEFORE,
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CPU_FEATURE_END
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);
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ASSERT_EFI_ERROR (Status);
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@ -107,7 +107,7 @@ CpuCommonFeaturesLibConstructor (
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VmxSupport,
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VmxInitialize,
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CPU_FEATURE_VMX,
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CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEFORE,
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CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_THREAD_BEFORE,
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CPU_FEATURE_END
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);
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ASSERT_EFI_ERROR (Status);
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@ -207,7 +207,7 @@ CpuCommonFeaturesLibConstructor (
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LmceSupport,
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LmceInitialize,
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CPU_FEATURE_LMCE,
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CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_BEFORE,
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CPU_FEATURE_LOCK_FEATURE_CONTROL_REGISTER | CPU_FEATURE_THREAD_BEFORE,
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CPU_FEATURE_END
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);
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ASSERT_EFI_ERROR (Status);
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@ -1,7 +1,7 @@
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/** @file
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CPU Register Table Library functions.
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Copyright (c) 2017 - 2019, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2017 - 2020, Intel Corporation. All rights reserved.<BR>
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SPDX-License-Identifier: BSD-2-Clause-Patent
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**/
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@ -858,16 +858,16 @@ RegisterCpuFeature (
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!= (CPU_FEATURE_CORE_BEFORE | CPU_FEATURE_CORE_AFTER));
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ASSERT ((Feature & (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER))
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!= (CPU_FEATURE_PACKAGE_BEFORE | CPU_FEATURE_PACKAGE_AFTER));
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if (Feature < CPU_FEATURE_BEFORE) {
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if (Feature < CPU_FEATURE_THREAD_BEFORE) {
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BeforeAll = ((Feature & CPU_FEATURE_BEFORE_ALL) != 0) ? TRUE : FALSE;
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AfterAll = ((Feature & CPU_FEATURE_AFTER_ALL) != 0) ? TRUE : FALSE;
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Feature &= ~(CPU_FEATURE_BEFORE_ALL | CPU_FEATURE_AFTER_ALL);
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ASSERT (FeatureMask == NULL);
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SetCpuFeaturesBitMask (&FeatureMask, Feature, CpuFeaturesData->BitMaskSize);
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} else if ((Feature & CPU_FEATURE_BEFORE) != 0) {
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SetCpuFeaturesBitMask (&BeforeFeatureBitMask, Feature & ~CPU_FEATURE_BEFORE, CpuFeaturesData->BitMaskSize);
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} else if ((Feature & CPU_FEATURE_AFTER) != 0) {
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SetCpuFeaturesBitMask (&AfterFeatureBitMask, Feature & ~CPU_FEATURE_AFTER, CpuFeaturesData->BitMaskSize);
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} else if ((Feature & CPU_FEATURE_THREAD_BEFORE) != 0) {
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SetCpuFeaturesBitMask (&BeforeFeatureBitMask, Feature & ~CPU_FEATURE_THREAD_BEFORE, CpuFeaturesData->BitMaskSize);
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} else if ((Feature & CPU_FEATURE_THREAD_AFTER) != 0) {
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SetCpuFeaturesBitMask (&AfterFeatureBitMask, Feature & ~CPU_FEATURE_THREAD_AFTER, CpuFeaturesData->BitMaskSize);
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} else if ((Feature & CPU_FEATURE_CORE_BEFORE) != 0) {
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SetCpuFeaturesBitMask (&CoreBeforeFeatureBitMask, Feature & ~CPU_FEATURE_CORE_BEFORE, CpuFeaturesData->BitMaskSize);
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} else if ((Feature & CPU_FEATURE_CORE_AFTER) != 0) {
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