mirror of https://github.com/acidanthera/audk.git
ArmPkg/ArmLib: Fixed TBLs invalidation in EL1
'tlb alle1' was used to invalidate the TLBs in EL1. Expect this instruction can only be invoked from EL2. The correct instruction to invalidate TLBs in EL1 is 'tlbi vmalle1' - it invalidates the TLBs of the current VMID. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin <olivier.martin@arm.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14509 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
parent
e21227c627
commit
70f89c0b5f
|
@ -123,7 +123,7 @@ ASM_PFX(ArmEnableMmu):
|
||||||
3: mrs x0, sctlr_el3 // Read System control register EL3
|
3: mrs x0, sctlr_el3 // Read System control register EL3
|
||||||
4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit
|
4: orr x0, x0, #CTRL_M_BIT // Set MMU enable bit
|
||||||
EL1_OR_EL2_OR_EL3(x1)
|
EL1_OR_EL2_OR_EL3(x1)
|
||||||
1: tlbi alle1
|
1: tlbi vmalle1
|
||||||
isb
|
isb
|
||||||
msr sctlr_el1, x0 // Write back
|
msr sctlr_el1, x0 // Write back
|
||||||
b 4f
|
b 4f
|
||||||
|
@ -149,7 +149,7 @@ ASM_PFX(ArmDisableMmu):
|
||||||
4: bic x0, x0, #CTRL_M_BIT // Clear MMU enable bit
|
4: bic x0, x0, #CTRL_M_BIT // Clear MMU enable bit
|
||||||
EL1_OR_EL2_OR_EL3(x1)
|
EL1_OR_EL2_OR_EL3(x1)
|
||||||
1: msr sctlr_el1, x0 // Write back
|
1: msr sctlr_el1, x0 // Write back
|
||||||
tlbi alle1
|
tlbi vmalle1
|
||||||
b 4f
|
b 4f
|
||||||
2: msr sctlr_el2, x0 // Write back
|
2: msr sctlr_el2, x0 // Write back
|
||||||
tlbi alle2
|
tlbi alle2
|
||||||
|
@ -441,7 +441,7 @@ ASM_PFX(ArmCallWFI):
|
||||||
|
|
||||||
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
|
ASM_PFX(ArmInvalidateInstructionAndDataTlb):
|
||||||
EL1_OR_EL2_OR_EL3(x0)
|
EL1_OR_EL2_OR_EL3(x0)
|
||||||
1: tlbi alle1
|
1: tlbi vmalle1
|
||||||
b 4f
|
b 4f
|
||||||
2: tlbi alle2
|
2: tlbi alle2
|
||||||
b 4f
|
b 4f
|
||||||
|
|
|
@ -167,7 +167,7 @@ ASM_PFX(ArmUpdateTranslationTableEntry):
|
||||||
|
|
||||||
ASM_PFX(ArmInvalidateTlb):
|
ASM_PFX(ArmInvalidateTlb):
|
||||||
EL1_OR_EL2_OR_EL3(x0)
|
EL1_OR_EL2_OR_EL3(x0)
|
||||||
1: tlbi alle1
|
1: tlbi vmalle1
|
||||||
b 4f
|
b 4f
|
||||||
2: tlbi alle2
|
2: tlbi alle2
|
||||||
b 4f
|
b 4f
|
||||||
|
|
Loading…
Reference in New Issue