mirror of https://github.com/acidanthera/audk.git
MdeModulePkg CapsuleX64: Reduce reserved memory consumption
We are going to reduce reserved memory consumption by page table buffer, then OS can have more available memory to use. Take PhysicalAddressBits = 48 and 2MB page granularity as example, 1:1 Virtual to Physical identity mapping page table buffer needs to be ((512 + 1) * 512 + 1) * 4096 = 1075843072 bytes = 0x40201000 bytes. The code is updated to build 4G page table by default and only use 8 extra pages to handles > 4G request by page fault. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Star Zeng <star.zeng@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@18069 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Star Zeng
lzeng14
parent
353f5ba92f
commit
716087e2be
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@ -9,7 +9,7 @@
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# This external input must be validated carefully to avoid security issue like
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# buffer overflow, integer overflow.
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#
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# Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
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#
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions
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@ -38,6 +38,8 @@
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[Sources]
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X64/X64Entry.c
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X64/PageFaultHandler.asm
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X64/PageFaultHandler.S
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Common/CapsuleCoalesce.c
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[Packages]
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@ -1,7 +1,7 @@
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/** @file
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Common header file.
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Copyright (c) 2011 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -15,6 +15,11 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#ifndef _CAPSULE_COMMON_HEADER_
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#define _CAPSULE_COMMON_HEADER_
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//
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// 8 extra pages for PF handler.
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//
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#define EXTRA_PAGE_TABLE_PAGES 8
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//
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// This capsule PEIM puts its private data at the start of the
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// coalesced capsule. Here's the structure definition.
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@ -33,6 +38,7 @@ typedef struct {
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#define CAPSULE_TEST_SIGNATURE SIGNATURE_32('T', 'E', 'S', 'T')
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#if defined (MDE_CPU_IA32) || defined (MDE_CPU_X64)
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#pragma pack(1)
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typedef struct {
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EFI_PHYSICAL_ADDRESS EntryPoint;
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EFI_PHYSICAL_ADDRESS StackBufferBase;
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@ -41,14 +47,23 @@ typedef struct {
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EFI_PHYSICAL_ADDRESS BlockListAddr;
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EFI_PHYSICAL_ADDRESS MemoryBase64Ptr;
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EFI_PHYSICAL_ADDRESS MemorySize64Ptr;
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BOOLEAN Page1GSupport;
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} SWITCH_32_TO_64_CONTEXT;
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typedef struct {
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UINT16 ReturnCs;
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EFI_PHYSICAL_ADDRESS ReturnEntryPoint;
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UINT64 ReturnStatus;
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//
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// NOTICE:
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// Be careful about the Base field of IA32_DESCRIPTOR
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// that is UINTN type.
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// To extend new field for this structure, add it to
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// right before this Gdtr field.
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//
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IA32_DESCRIPTOR Gdtr;
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} SWITCH_64_TO_32_CONTEXT;
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#pragma pack()
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#endif
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/**
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@ -42,24 +42,19 @@ GLOBAL_REMOVE_IF_UNREFERENCED CONST IA32_DESCRIPTOR mGdt = {
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};
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/**
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Calculate the total size of page table.
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@return The size of page table.
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The function will check if 1G page is supported.
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@retval TRUE 1G page is supported.
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@retval FALSE 1G page is not supported.
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**/
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UINTN
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CalculatePageTableSize (
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BOOLEAN
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IsPage1GSupport (
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VOID
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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UINTN TotalPagesNum;
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UINT8 PhysicalAddressBits;
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VOID *Hob;
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UINT32 NumberOfPml4EntriesNeeded;
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UINT32 NumberOfPdpEntriesNeeded;
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BOOLEAN Page1GSupport;
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Page1GSupport = FALSE;
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@ -73,29 +68,34 @@ CalculatePageTableSize (
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}
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}
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//
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// Get physical address bits supported.
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//
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Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
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if (Hob != NULL) {
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PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
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} else {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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PhysicalAddressBits = (UINT8) RegEax;
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} else {
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PhysicalAddressBits = 36;
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}
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}
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return Page1GSupport;
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}
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/**
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Calculate the total size of page table.
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@param[in] Page1GSupport 1G page support or not.
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@return The size of page table.
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**/
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UINTN
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CalculatePageTableSize (
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IN BOOLEAN Page1GSupport
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)
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{
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UINTN ExtraPageTablePages;
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UINTN TotalPagesNum;
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UINT8 PhysicalAddressBits;
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UINT32 NumberOfPml4EntriesNeeded;
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UINT32 NumberOfPdpEntriesNeeded;
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//
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// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
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// Create 4G page table by default,
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// and let PF handler to handle > 4G request.
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//
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ASSERT (PhysicalAddressBits <= 52);
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if (PhysicalAddressBits > 48) {
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PhysicalAddressBits = 48;
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}
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PhysicalAddressBits = 32;
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ExtraPageTablePages = EXTRA_PAGE_TABLE_PAGES;
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//
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// Calculate the table entries needed.
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@ -113,24 +113,25 @@ CalculatePageTableSize (
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} else {
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TotalPagesNum = NumberOfPml4EntriesNeeded + 1;
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}
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TotalPagesNum += ExtraPageTablePages;
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return EFI_PAGES_TO_SIZE (TotalPagesNum);
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}
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/**
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Allocates and fills in the Page Directory and Page Table Entries to
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establish a 1:1 Virtual to Physical mapping.
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establish a 4G page table.
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@param[in] PageTablesAddress The base address of page table.
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@param[in] Page1GSupport 1G page support or not.
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**/
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VOID
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CreateIdentityMappingPageTables (
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IN EFI_PHYSICAL_ADDRESS PageTablesAddress
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Create4GPageTables (
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IN EFI_PHYSICAL_ADDRESS PageTablesAddress,
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IN BOOLEAN Page1GSupport
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)
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{
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UINT32 RegEax;
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UINT32 RegEdx;
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UINT8 PhysicalAddressBits;
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EFI_PHYSICAL_ADDRESS PageAddress;
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UINTN IndexOfPml4Entries;
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@ -143,42 +144,13 @@ CreateIdentityMappingPageTables (
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PAGE_MAP_AND_DIRECTORY_POINTER *PageDirectoryPointerEntry;
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PAGE_TABLE_ENTRY *PageDirectoryEntry;
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UINTN BigPageAddress;
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VOID *Hob;
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BOOLEAN Page1GSupport;
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PAGE_TABLE_1G_ENTRY *PageDirectory1GEntry;
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Page1GSupport = FALSE;
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000001) {
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AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);
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if ((RegEdx & BIT26) != 0) {
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Page1GSupport = TRUE;
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}
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}
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//
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// Get physical address bits supported.
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// Create 4G page table by default,
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// and let PF handler to handle > 4G request.
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//
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Hob = GetFirstHob (EFI_HOB_TYPE_CPU);
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if (Hob != NULL) {
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PhysicalAddressBits = ((EFI_HOB_CPU *) Hob)->SizeOfMemorySpace;
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} else {
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AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
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if (RegEax >= 0x80000008) {
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AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
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PhysicalAddressBits = (UINT8) RegEax;
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} else {
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PhysicalAddressBits = 36;
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}
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}
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//
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// IA-32e paging translates 48-bit linear addresses to 52-bit physical addresses.
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//
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ASSERT (PhysicalAddressBits <= 52);
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if (PhysicalAddressBits > 48) {
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PhysicalAddressBits = 48;
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}
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PhysicalAddressBits = 32;
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//
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// Calculate the table entries needed.
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@ -335,9 +307,9 @@ Thunk32To64 (
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if (SetJumpFlag == 0) {
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//
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// Build Page Tables for all physical memory processor supports
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// Build 4G Page Tables.
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//
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CreateIdentityMappingPageTables (PageTableAddress);
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Create4GPageTables (PageTableAddress, Context->Page1GSupport);
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//
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// Create 64-bit GDT
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@ -407,6 +379,7 @@ ModeSwitch (
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BASE_LIBRARY_JUMP_BUFFER JumpBuffer;
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EFI_PHYSICAL_ADDRESS ReservedRangeBase;
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EFI_PHYSICAL_ADDRESS ReservedRangeEnd;
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BOOLEAN Page1GSupport;
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ZeroMem (&Context, sizeof (SWITCH_32_TO_64_CONTEXT));
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ZeroMem (&ReturnContext, sizeof (SWITCH_64_TO_32_CONTEXT));
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@ -415,12 +388,14 @@ ModeSwitch (
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MemorySize64 = (UINT64) (UINTN) *MemorySize;
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MemoryEnd64 = MemoryBase64 + MemorySize64;
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Page1GSupport = IsPage1GSupport ();
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//
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// Merge memory range reserved for stack and page table
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//
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if (LongModeBuffer->StackBaseAddress < LongModeBuffer->PageTableAddress) {
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ReservedRangeBase = LongModeBuffer->StackBaseAddress;
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ReservedRangeEnd = LongModeBuffer->PageTableAddress + CalculatePageTableSize ();
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ReservedRangeEnd = LongModeBuffer->PageTableAddress + CalculatePageTableSize (Page1GSupport);
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} else {
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ReservedRangeBase = LongModeBuffer->PageTableAddress;
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ReservedRangeEnd = LongModeBuffer->StackBaseAddress + LongModeBuffer->StackSize;
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@ -456,6 +431,7 @@ ModeSwitch (
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Context.BlockListAddr = BlockListAddr;
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Context.MemoryBase64Ptr = (EFI_PHYSICAL_ADDRESS)(UINTN)&MemoryBase64;
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Context.MemorySize64Ptr = (EFI_PHYSICAL_ADDRESS)(UINTN)&MemorySize64;
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Context.Page1GSupport = Page1GSupport;
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//
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// Prepare data for return back
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@ -529,7 +505,7 @@ FindCapsuleCoalesceImage (
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&AuthenticationState
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);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "Unable to find PE32 section in CapsuleRelocate image ffs %r!\n", Status));
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DEBUG ((EFI_D_ERROR, "Unable to find PE32 section in CapsuleX64 image ffs %r!\n", Status));
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return Status;
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}
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*CoalesceImageMachineType = PeCoffLoaderGetMachineType ((VOID *) (UINTN) CoalesceImageAddress);
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@ -542,6 +518,46 @@ FindCapsuleCoalesceImage (
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return Status;
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}
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/**
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Gets the reserved long mode buffer.
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@param LongModeBuffer Pointer to the long mode buffer for output.
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@retval EFI_SUCCESS Long mode buffer successfully retrieved.
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@retval Others Variable storing long mode buffer not found.
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**/
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EFI_STATUS
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GetLongModeContext (
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OUT EFI_CAPSULE_LONG_MODE_BUFFER *LongModeBuffer
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)
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{
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EFI_STATUS Status;
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UINTN Size;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *PPIVariableServices;
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Status = PeiServicesLocatePpi (
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&gEfiPeiReadOnlyVariable2PpiGuid,
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0,
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NULL,
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(VOID **) &PPIVariableServices
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);
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ASSERT_EFI_ERROR (Status);
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Size = sizeof (EFI_CAPSULE_LONG_MODE_BUFFER);
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Status = PPIVariableServices->GetVariable (
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PPIVariableServices,
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EFI_CAPSULE_LONG_MODE_BUFFER_NAME,
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&gEfiCapsuleVendorGuid,
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NULL,
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&Size,
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LongModeBuffer
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);
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if (EFI_ERROR (Status)) {
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DEBUG (( EFI_D_ERROR, "Error Get LongModeBuffer variable %r!\n", Status));
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}
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return Status;
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}
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#endif
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/**
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@ -654,47 +670,6 @@ GetCapsuleDescriptors (
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return EFI_SUCCESS;
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}
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/**
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Gets the reserved long mode buffer.
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@param LongModeBuffer Pointer to the long mode buffer for output.
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@retval EFI_SUCCESS Long mode buffer successfully retrieved.
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@retval Others Variable storing long mode buffer not found.
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**/
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EFI_STATUS
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GetLongModeContext (
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OUT EFI_CAPSULE_LONG_MODE_BUFFER *LongModeBuffer
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)
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{
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EFI_STATUS Status;
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UINTN Size;
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EFI_PEI_READ_ONLY_VARIABLE2_PPI *PPIVariableServices;
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Status = PeiServicesLocatePpi (
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&gEfiPeiReadOnlyVariable2PpiGuid,
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0,
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NULL,
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(VOID **) &PPIVariableServices
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);
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ASSERT_EFI_ERROR (Status);
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Size = sizeof (EFI_CAPSULE_LONG_MODE_BUFFER);
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Status = PPIVariableServices->GetVariable (
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PPIVariableServices,
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EFI_CAPSULE_LONG_MODE_BUFFER_NAME,
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&gEfiCapsuleVendorGuid,
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NULL,
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&Size,
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LongModeBuffer
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);
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if (EFI_ERROR (Status)) {
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DEBUG (( EFI_D_ERROR, "Error Get LongModeBuffer variable %r!\n", Status));
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}
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return Status;
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}
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/**
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Capsule PPI service to coalesce a fragmented capsule in memory.
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@ -837,7 +812,7 @@ CapsuleCoalesce (
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CoalesceImageEntryPoint = 0;
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Status = GetLongModeContext (&LongModeBuffer);
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if (EFI_ERROR (Status)) {
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DEBUG ((EFI_D_ERROR, "Fail to find the variables for long mode context!\n"));
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DEBUG ((EFI_D_ERROR, "Fail to find the variable for long mode context!\n"));
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Status = EFI_NOT_FOUND;
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goto Done;
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}
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|
|
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|
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@ -0,0 +1,81 @@
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## @file
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# This is the assembly code for page fault handler hook.
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#
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# Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
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#
|
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# This program and the accompanying materials are
|
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# licensed and made available under the terms and conditions of the BSD License
|
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# which accompanies this distribution. The full text of the license may be found at
|
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# http://opensource.org/licenses/bsd-license.php
|
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#
|
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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##
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ASM_GLOBAL ASM_PFX(PageFaultHandlerHook)
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ASM_PFX(PageFaultHandlerHook):
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addq $-0x10, %rsp
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# save rax
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movq %rax, 0x08(%rsp)
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# pushq %rax # save all volatile registers
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pushq %rcx
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pushq %rdx
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pushq %r8
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pushq %r9
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pushq %r10
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pushq %r11
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# save volatile fp registers
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# 68h + 08h(for alignment)
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addq $-0x70, %rsp
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stmxcsr 0x60(%rsp)
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movdqa %xmm0, 0x0(%rsp)
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movdqa %xmm1, 0x10(%rsp)
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movdqa %xmm2, 0x20(%rsp)
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movdqa %xmm3, 0x30(%rsp)
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movdqa %xmm4, 0x40(%rsp)
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movdqa %xmm5, 0x50(%rsp)
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addq $-0x20, %rsp
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call ASM_PFX(PageFaultHandler)
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addq $0x20, %rsp
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# load volatile fp registers
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ldmxcsr 0x60(%rsp)
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movdqa 0x0(%rsp), %xmm0
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movdqa 0x10(%rsp), %xmm1
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movdqa 0x20(%rsp), %xmm2
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movdqa 0x30(%rsp), %xmm3
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movdqa 0x40(%rsp), %xmm4
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movdqa 0x50(%rsp), %xmm5
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addq $0x70, %rsp
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popq %r11
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popq %r10
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popq %r9
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popq %r8
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popq %rdx
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popq %rcx
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# popq %rax # restore all volatile registers
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|
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addq $0x10, %rsp
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|
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# rax returned from PageFaultHandler is NULL or OriginalHandler address
|
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# NULL if the page fault is handled by PageFaultHandler
|
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# OriginalHandler address if the page fault is not handled by PageFaultHandler
|
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testq %rax, %rax
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# save OriginalHandler address
|
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movq %rax, -0x10(%rsp)
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# restore rax
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movq -0x08(%rsp), %rax
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|
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jz L1
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|
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# jump to OriginalHandler
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jmpq *-0x10(%rsp)
|
||||
|
||||
L1:
|
||||
addq $0x08, %rsp # skip error code for PF
|
||||
iretq
|
||||
|
|
@ -0,0 +1,87 @@
|
|||
;; @file
|
||||
; This is the assembly code for page fault handler hook.
|
||||
;
|
||||
; Copyright (c) 2015, Intel Corporation. All rights reserved.<BR>
|
||||
;
|
||||
; This program and the accompanying materials
|
||||
; are licensed and made available under the terms and conditions of the BSD License
|
||||
; which accompanies this distribution. The full text of the license may be found at
|
||||
; http://opensource.org/licenses/bsd-license.php
|
||||
;
|
||||
; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
;
|
||||
;;
|
||||
|
||||
EXTERN PageFaultHandler:PROC
|
||||
|
||||
.code
|
||||
|
||||
PageFaultHandlerHook PROC
|
||||
add rsp, -10h
|
||||
; save rax
|
||||
mov [rsp + 08h], rax
|
||||
|
||||
;push rax ; save all volatile registers
|
||||
push rcx
|
||||
push rdx
|
||||
push r8
|
||||
push r9
|
||||
push r10
|
||||
push r11
|
||||
; save volatile fp registers
|
||||
; 68h + 08h(for alignment)
|
||||
add rsp, -70h
|
||||
stmxcsr [rsp + 60h]
|
||||
movdqa [rsp + 0h], xmm0
|
||||
movdqa [rsp + 10h], xmm1
|
||||
movdqa [rsp + 20h], xmm2
|
||||
movdqa [rsp + 30h], xmm3
|
||||
movdqa [rsp + 40h], xmm4
|
||||
movdqa [rsp + 50h], xmm5
|
||||
|
||||
add rsp, -20h
|
||||
call PageFaultHandler
|
||||
add rsp, 20h
|
||||
|
||||
; load volatile fp registers
|
||||
ldmxcsr [rsp + 60h]
|
||||
movdqa xmm0, [rsp + 0h]
|
||||
movdqa xmm1, [rsp + 10h]
|
||||
movdqa xmm2, [rsp + 20h]
|
||||
movdqa xmm3, [rsp + 30h]
|
||||
movdqa xmm4, [rsp + 40h]
|
||||
movdqa xmm5, [rsp + 50h]
|
||||
add rsp, 70h
|
||||
|
||||
pop r11
|
||||
pop r10
|
||||
pop r9
|
||||
pop r8
|
||||
pop rdx
|
||||
pop rcx
|
||||
;pop rax ; restore all volatile registers
|
||||
|
||||
add rsp, 10h
|
||||
|
||||
; rax returned from PageFaultHandler is NULL or OriginalHandler address
|
||||
; NULL if the page fault is handled by PageFaultHandler
|
||||
; OriginalHandler address if the page fault is not handled by PageFaultHandler
|
||||
test rax, rax
|
||||
|
||||
; save OriginalHandler address
|
||||
mov [rsp - 10h], rax
|
||||
; restore rax
|
||||
mov rax, [rsp - 08h]
|
||||
|
||||
jz @F
|
||||
|
||||
; jump to OriginalHandler
|
||||
jmp qword ptr [rsp - 10h]
|
||||
|
||||
@@:
|
||||
add rsp, 08h ; skip error code for PF
|
||||
iretq
|
||||
PageFaultHandlerHook ENDP
|
||||
|
||||
END
|
||||
|
|
@ -1,7 +1,7 @@
|
|||
/** @file
|
||||
The X64 entrypoint is used to process capsule in long mode.
|
||||
|
||||
Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>
|
||||
Copyright (c) 2011 - 2015, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials
|
||||
are licensed and made available under the terms and conditions of the BSD License
|
||||
which accompanies this distribution. The full text of the license may be found at
|
||||
|
|
@ -20,6 +20,184 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
|||
|
||||
#define EXCEPTION_VECTOR_NUMBER 0x22
|
||||
|
||||
#define IA32_PG_P BIT0
|
||||
#define IA32_PG_RW BIT1
|
||||
#define IA32_PG_PS BIT7
|
||||
|
||||
typedef struct _PAGE_FAULT_CONTEXT {
|
||||
BOOLEAN Page1GSupport;
|
||||
UINT64 PhyMask;
|
||||
UINTN PageFaultBuffer;
|
||||
UINTN PageFaultIndex;
|
||||
//
|
||||
// Store the uplink information for each page being used.
|
||||
//
|
||||
UINT64 *PageFaultUplink[EXTRA_PAGE_TABLE_PAGES];
|
||||
VOID *OriginalHandler;
|
||||
} PAGE_FAULT_CONTEXT;
|
||||
|
||||
typedef struct _PAGE_FAULT_IDT_TABLE {
|
||||
PAGE_FAULT_CONTEXT PageFaultContext;
|
||||
IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
|
||||
} PAGE_FAULT_IDT_TABLE;
|
||||
|
||||
/**
|
||||
Page fault handler.
|
||||
|
||||
**/
|
||||
VOID
|
||||
EFIAPI
|
||||
PageFaultHandlerHook (
|
||||
VOID
|
||||
);
|
||||
|
||||
/**
|
||||
Hook IDT with our page fault handler so that the on-demand paging works on page fault.
|
||||
|
||||
@param[in, out] IdtEntry Pointer to IDT entry.
|
||||
@param[in, out] PageFaultContext Pointer to page fault context.
|
||||
|
||||
**/
|
||||
VOID
|
||||
HookPageFaultHandler (
|
||||
IN OUT IA32_IDT_GATE_DESCRIPTOR *IdtEntry,
|
||||
IN OUT PAGE_FAULT_CONTEXT *PageFaultContext
|
||||
)
|
||||
{
|
||||
UINT32 RegEax;
|
||||
UINT8 PhysicalAddressBits;
|
||||
UINTN PageFaultHandlerHookAddress;
|
||||
|
||||
AsmCpuid (0x80000000, &RegEax, NULL, NULL, NULL);
|
||||
if (RegEax >= 0x80000008) {
|
||||
AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);
|
||||
PhysicalAddressBits = (UINT8) RegEax;
|
||||
} else {
|
||||
PhysicalAddressBits = 36;
|
||||
}
|
||||
PageFaultContext->PhyMask = LShiftU64 (1, PhysicalAddressBits) - 1;
|
||||
PageFaultContext->PhyMask &= (1ull << 48) - SIZE_4KB;
|
||||
|
||||
//
|
||||
// Set Page Fault entry to catch >4G access
|
||||
//
|
||||
PageFaultHandlerHookAddress = (UINTN)PageFaultHandlerHook;
|
||||
PageFaultContext->OriginalHandler = (VOID *)(UINTN)(LShiftU64 (IdtEntry->Bits.OffsetUpper, 32) + IdtEntry->Bits.OffsetLow + (IdtEntry->Bits.OffsetHigh << 16));
|
||||
IdtEntry->Bits.OffsetLow = (UINT16)PageFaultHandlerHookAddress;
|
||||
IdtEntry->Bits.Selector = (UINT16)AsmReadCs ();
|
||||
IdtEntry->Bits.Reserved_0 = 0;
|
||||
IdtEntry->Bits.GateType = IA32_IDT_GATE_TYPE_INTERRUPT_32;
|
||||
IdtEntry->Bits.OffsetHigh = (UINT16)(PageFaultHandlerHookAddress >> 16);
|
||||
IdtEntry->Bits.OffsetUpper = (UINT32)(PageFaultHandlerHookAddress >> 32);
|
||||
IdtEntry->Bits.Reserved_1 = 0;
|
||||
|
||||
if (PageFaultContext->Page1GSupport) {
|
||||
PageFaultContext->PageFaultBuffer = (UINTN)(AsmReadCr3 () & PageFaultContext->PhyMask) + EFI_PAGES_TO_SIZE(2);
|
||||
}else {
|
||||
PageFaultContext->PageFaultBuffer = (UINTN)(AsmReadCr3 () & PageFaultContext->PhyMask) + EFI_PAGES_TO_SIZE(6);
|
||||
}
|
||||
PageFaultContext->PageFaultIndex = 0;
|
||||
ZeroMem (PageFaultContext->PageFaultUplink, sizeof (PageFaultContext->PageFaultUplink));
|
||||
}
|
||||
|
||||
/**
|
||||
Acquire page for page fault.
|
||||
|
||||
@param[in, out] PageFaultContext Pointer to page fault context.
|
||||
@param[in, out] Uplink Pointer to up page table entry.
|
||||
|
||||
**/
|
||||
VOID
|
||||
AcquirePage (
|
||||
IN OUT PAGE_FAULT_CONTEXT *PageFaultContext,
|
||||
IN OUT UINT64 *Uplink
|
||||
)
|
||||
{
|
||||
UINTN Address;
|
||||
|
||||
Address = PageFaultContext->PageFaultBuffer + EFI_PAGES_TO_SIZE (PageFaultContext->PageFaultIndex);
|
||||
ZeroMem ((VOID *) Address, EFI_PAGES_TO_SIZE (1));
|
||||
|
||||
//
|
||||
// Cut the previous uplink if it exists and wasn't overwritten.
|
||||
//
|
||||
if ((PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] != NULL) && ((*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] & PageFaultContext->PhyMask) == Address)) {
|
||||
*PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = 0;
|
||||
}
|
||||
|
||||
//
|
||||
// Link & Record the current uplink.
|
||||
//
|
||||
*Uplink = Address | IA32_PG_P | IA32_PG_RW;
|
||||
PageFaultContext->PageFaultUplink[PageFaultContext->PageFaultIndex] = Uplink;
|
||||
|
||||
PageFaultContext->PageFaultIndex = (PageFaultContext->PageFaultIndex + 1) % EXTRA_PAGE_TABLE_PAGES;
|
||||
}
|
||||
|
||||
/**
|
||||
The page fault handler that on-demand read >4G memory/MMIO.
|
||||
|
||||
@retval NULL The page fault is correctly handled.
|
||||
@retval OriginalHandler The page fault is not handled and is passed through to original handler.
|
||||
|
||||
**/
|
||||
VOID *
|
||||
EFIAPI
|
||||
PageFaultHandler (
|
||||
VOID
|
||||
)
|
||||
{
|
||||
IA32_DESCRIPTOR Idtr;
|
||||
PAGE_FAULT_CONTEXT *PageFaultContext;
|
||||
UINT64 PhyMask;
|
||||
UINT64 *PageTable;
|
||||
UINT64 PFAddress;
|
||||
UINTN PTIndex;
|
||||
|
||||
//
|
||||
// Get the IDT Descriptor.
|
||||
//
|
||||
AsmReadIdtr ((IA32_DESCRIPTOR *) &Idtr);
|
||||
//
|
||||
// Then get page fault context by IDT Descriptor.
|
||||
//
|
||||
PageFaultContext = (PAGE_FAULT_CONTEXT *) (UINTN) (Idtr.Base - sizeof (PAGE_FAULT_CONTEXT));
|
||||
PhyMask = PageFaultContext->PhyMask;
|
||||
|
||||
PFAddress = AsmReadCr2 ();
|
||||
DEBUG ((EFI_D_ERROR, "CapsuleX64 - PageFaultHandler: Cr2 - %lx\n", PFAddress));
|
||||
|
||||
if (PFAddress >= PhyMask + SIZE_4KB) {
|
||||
return PageFaultContext->OriginalHandler;
|
||||
}
|
||||
PFAddress &= PhyMask;
|
||||
|
||||
PageTable = (UINT64*)(UINTN)(AsmReadCr3 () & PhyMask);
|
||||
|
||||
PTIndex = BitFieldRead64 (PFAddress, 39, 47);
|
||||
// PML4E
|
||||
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
|
||||
AcquirePage (PageFaultContext, &PageTable[PTIndex]);
|
||||
}
|
||||
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask);
|
||||
PTIndex = BitFieldRead64 (PFAddress, 30, 38);
|
||||
// PDPTE
|
||||
if (PageFaultContext->Page1GSupport) {
|
||||
PageTable[PTIndex] = (PFAddress & ~((1ull << 30) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
|
||||
} else {
|
||||
if ((PageTable[PTIndex] & IA32_PG_P) == 0) {
|
||||
AcquirePage (PageFaultContext, &PageTable[PTIndex]);
|
||||
}
|
||||
PageTable = (UINT64*)(UINTN)(PageTable[PTIndex] & PhyMask);
|
||||
PTIndex = BitFieldRead64 (PFAddress, 21, 29);
|
||||
// PD
|
||||
PageTable[PTIndex] = (PFAddress & ~((1ull << 21) - 1)) | IA32_PG_P | IA32_PG_RW | IA32_PG_PS;
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
|
||||
/**
|
||||
The X64 entrypoint is used to process capsule in long mode then
|
||||
return to 32-bit protected mode.
|
||||
|
|
@ -40,7 +218,8 @@ _ModuleEntryPoint (
|
|||
EFI_STATUS Status;
|
||||
IA32_DESCRIPTOR Ia32Idtr;
|
||||
IA32_DESCRIPTOR X64Idtr;
|
||||
IA32_IDT_GATE_DESCRIPTOR IdtEntryTable[EXCEPTION_VECTOR_NUMBER];
|
||||
PAGE_FAULT_IDT_TABLE PageFaultIdtTable;
|
||||
IA32_IDT_GATE_DESCRIPTOR *IdtEntry;
|
||||
|
||||
//
|
||||
// Save the IA32 IDT Descriptor
|
||||
|
|
@ -50,8 +229,8 @@ _ModuleEntryPoint (
|
|||
//
|
||||
// Setup X64 IDT table
|
||||
//
|
||||
ZeroMem (IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * EXCEPTION_VECTOR_NUMBER);
|
||||
X64Idtr.Base = (UINTN) IdtEntryTable;
|
||||
ZeroMem (PageFaultIdtTable.IdtEntryTable, sizeof (IA32_IDT_GATE_DESCRIPTOR) * EXCEPTION_VECTOR_NUMBER);
|
||||
X64Idtr.Base = (UINTN) PageFaultIdtTable.IdtEntryTable;
|
||||
X64Idtr.Limit = (UINT16) (sizeof (IA32_IDT_GATE_DESCRIPTOR) * EXCEPTION_VECTOR_NUMBER - 1);
|
||||
AsmWriteIdtr ((IA32_DESCRIPTOR *) &X64Idtr);
|
||||
|
||||
|
|
@ -61,6 +240,13 @@ _ModuleEntryPoint (
|
|||
Status = InitializeCpuExceptionHandlers (NULL);
|
||||
ASSERT_EFI_ERROR (Status);
|
||||
|
||||
//
|
||||
// Hook page fault handler to handle >4G request.
|
||||
//
|
||||
PageFaultIdtTable.PageFaultContext.Page1GSupport = EntrypointContext->Page1GSupport;
|
||||
IdtEntry = (IA32_IDT_GATE_DESCRIPTOR *) (X64Idtr.Base + (14 * sizeof (IA32_IDT_GATE_DESCRIPTOR)));
|
||||
HookPageFaultHandler (IdtEntry, &(PageFaultIdtTable.PageFaultContext));
|
||||
|
||||
//
|
||||
// Initialize Debug Agent to support source level debug
|
||||
//
|
||||
|
|
|
|||
Loading…
Reference in New Issue