mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg: Fix PL011 FIFO size test
This change updates PL011UartInitializePort to compare ReceiveFifoDepth with the correct hardware FIFO size instead of the constant 32 used previously. This corrects a minor bug where a request for a fifo size > 15 and < 32 would not have been honoured on a system with a 16 byte FIFO. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Evan Lloyd <evan.lloyd@arm.com> Reviewed-by: Leif Lindholm <leif.lindholm@linaro.org>
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@ -79,17 +79,18 @@ PL011UartInitializePort (
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UINT32 Divisor;
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UINT32 Divisor;
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UINT32 Integer;
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UINT32 Integer;
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UINT32 Fractional;
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UINT32 Fractional;
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UINT32 HardwareFifoDepth;
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HardwareFifoDepth = (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) \
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> PL011_VER_R1P4) \
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? 32 : 16 ;
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// The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept
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// The PL011 supports a buffer of 1, 16 or 32 chars. Therefore we can accept
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// 1 char buffer as the minimum FIFO size. Because everything can be rounded
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// 1 char buffer as the minimum FIFO size. Because everything can be rounded
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// down, there is no maximum FIFO size.
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// down, there is no maximum FIFO size.
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if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= 32)) {
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if ((*ReceiveFifoDepth == 0) || (*ReceiveFifoDepth >= HardwareFifoDepth)) {
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// Enable FIFO
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// Enable FIFO
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LineControl = PL011_UARTLCR_H_FEN;
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LineControl = PL011_UARTLCR_H_FEN;
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if (PL011_UARTPID2_VER (MmioRead32 (UartBase + UARTPID2)) > PL011_VER_R1P4)
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*ReceiveFifoDepth = HardwareFifoDepth;
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*ReceiveFifoDepth = 32;
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else
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*ReceiveFifoDepth = 16;
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} else {
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} else {
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// Disable FIFO
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// Disable FIFO
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LineControl = 0;
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LineControl = 0;
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