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MdeModulePkg/DxeIplPeim: fix PcdUse5LevelPageTable assert 

PcdUse5LevelPageTable documentation says:

  Indicates if 5-Level Paging will be enabled in long mode. 5-Level
  Paging will not be enabled when the PCD is TRUE but CPU doesn't support
  5-Level Paging.

So running in 4-level paging mode with PcdUse5LevelPageTable=TRUE is
possible.  The only invalid combination is 5-level paging being active
with PcdUse5LevelPageTable=FALSE.

Fix the ASSERT accordingly.

Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Reviewed-by: Laszlo Ersek <lersek@redhat.com>
Acked-by: Ard Biesheuvel <ardb@kernel.org>
Message-Id: <20240222105407.75735-2-kraxel@redhat.com>
Cc: Michael Roth <michael.roth@amd.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Tom Lendacky <thomas.lendacky@amd.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ard Biesheuvel <ardb+tianocore@kernel.org>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Min Xu <min.m.xu@intel.com>
Cc: Erdem Aktas <erdemaktas@google.com>
Cc: Oliver Steffen <osteffen@redhat.com>
Cc: Ard Biesheuvel <ardb@kernel.org>
[lersek@redhat.com: turn the "Cc:" message headers from Gerd's on-list
 posting into "Cc:" tags in the commit message, in order to pacify
 "PatchCheck.py"]
This commit is contained in:
Gerd Hoffmann 2024-02-22 11:54:05 +01:00 committed by mergify[bot]
parent d9a6e7b0b8
commit 73ac735be8
1 changed files with 3 additions and 1 deletions
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4
MdeModulePkg/Core/DxeIplPeim/X64/VirtualMemory.c
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@ -745,7 +745,9 @@ CreateIdentityMappingPageTables (
// //
Cr4.UintN = AsmReadCr4 (); Cr4.UintN = AsmReadCr4 ();
Page5LevelSupport = (Cr4.Bits.LA57 != 0); Page5LevelSupport = (Cr4.Bits.LA57 != 0);
ASSERT (PcdGetBool (PcdUse5LevelPageTable) == Page5LevelSupport); if (Page5LevelSupport) {
ASSERT (PcdGetBool (PcdUse5LevelPageTable));
}
} else { } else {
// //
// If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability. // If cpu runs in 32bit protected mode PEI, Page table Level in DXE is decided by PCD and feature capability.