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MdeModulePkg XhciDxe: Set HSEE Bit if SERR# Enable Bit is set

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1167

When the HSEE in the USBCMD bit is a ‘1’ and the HSE bit in the
USBSTS register is a ‘1’, the xHC shall assert out-of-band error
signaling to the host and assert the SERR# pin.
To prevent masking any potential issues with SERR, this patch is
to set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR#
Enable Bit is set.

Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Fei1 Wang <fei1.wang@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
This commit is contained in:
Star Zeng 2018-09-05 08:54:54 +08:00
parent 84a52d4d03
commit 73dbd6afab
1 changed files with 41 additions and 0 deletions
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41
MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.c
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@ -586,6 +586,39 @@ XhcIsSysError (
return XHC_REG_BIT_IS_SET (Xhc, XHC_USBSTS_OFFSET, XHC_USBSTS_HSE);
}
/**
Set USBCMD Host System Error Enable(HSEE) Bit if PCICMD SERR# Enable Bit is set.
The USBCMD HSEE Bit will be reset to default 0 by USBCMD Host Controller Reset(HCRST).
This function is to set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.
@param Xhc The XHCI Instance.
**/
VOID
XhcSetHsee (
IN USB_XHCI_INSTANCE *Xhc
)
{
EFI_STATUS Status;
EFI_PCI_IO_PROTOCOL *PciIo;
UINT16 XhciCmd;
PciIo = Xhc->PciIo;
Status = PciIo->Pci.Read (
PciIo,
EfiPciIoWidthUint16,
PCI_COMMAND_OFFSET,
sizeof (XhciCmd),
&XhciCmd
);
if (!EFI_ERROR (Status)) {
if ((XhciCmd & EFI_PCI_COMMAND_SERR) != 0) {
XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_HSEE);
}
}
}
/**
Reset the XHCI host controller.
@ -628,6 +661,14 @@ XhcResetHC (
//
gBS->Stall (XHC_1_MILLISECOND);
Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
if (!EFI_ERROR (Status)) {
//
// The USBCMD HSEE Bit will be reset to default 0 by USBCMD HCRST.
// Set USBCMD HSEE Bit if PCICMD SERR# Enable Bit is set.
//
XhcSetHsee (Xhc);
}
}
return Status;