From 748fea6279efc20de3fef483deb4b774f3c34906 Mon Sep 17 00:00:00 2001 From: Ard Biesheuvel Date: Sat, 7 Mar 2020 09:38:49 +0100 Subject: [PATCH] ArmPkg/ArmMmuLib AARCH64: invalidate page tables before populating them As it turns out, ARMv8 also permits accesses made with the MMU and caches off to hit in the caches, so to ensure that any modifications we make before enabling the MMU are visible afterwards as well, we should invalidate page tables right after allocation like we do now on ARM, if the MMU is still disabled at that point. Signed-off-by: Ard Biesheuvel Reviewed-by: Leif Lindholm Message-Id: <20200307083849.8940-3-ard.biesheuvel@linaro.org> --- ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c index 00a38bc31d..221175ca65 100644 --- a/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c +++ b/ArmPkg/Library/ArmMmuLib/AArch64/ArmMmuLibCore.c @@ -204,6 +204,14 @@ UpdateRegionMappingRecursive ( return EFI_OUT_OF_RESOURCES; } + if (!ArmMmuEnabled ()) { + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange (TranslationTable, EFI_PAGE_SIZE); + } + if ((*Entry & TT_TYPE_MASK) == TT_TYPE_BLOCK_ENTRY) { // // We are splitting an existing block entry, so we have to populate @@ -602,6 +610,12 @@ ArmConfigureMmu ( *TranslationTableSize = RootTableEntryCount * sizeof(UINT64); } + // + // Make sure we are not inadvertently hitting in the caches + // when populating the page tables. + // + InvalidateDataCacheRange (TranslationTable, + RootTableEntryCount * sizeof(UINT64)); ZeroMem (TranslationTable, RootTableEntryCount * sizeof(UINT64)); TranslationTableAttribute = TT_ATTR_INDX_INVALID;