mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/XhciDxe: Usb legacy support feature is optional. For those usb 3.0 devices which doesn’t support this feature, should directly return and not touch corresponding registers
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Sergey Isakov <isakov-sl@bk.ru> Signed-off-by: Tian, Feng <feng.tian@intel.com> Reviewed-by: Li, Elvin <elvin.li@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14776 6f19259b-4bc3-4df7-8a09-765794883524
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@ -164,7 +164,7 @@ XhcReset (
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// Flow through, same behavior as Host Controller Reset
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// Flow through, same behavior as Host Controller Reset
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//
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//
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case EFI_USB_HC_RESET_HOST_CONTROLLER:
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case EFI_USB_HC_RESET_HOST_CONTROLLER:
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if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
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if ((Xhc->DebugCapSupOffset != 0xFFFFFFFF) && ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) == XHC_CAP_USB_DEBUG) &&
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((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {
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((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) != 0)) {
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Status = EFI_SUCCESS;
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Status = EFI_SUCCESS;
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goto ON_EXIT;
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goto ON_EXIT;
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@ -543,6 +543,10 @@ XhcSetBiosOwnership (
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{
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{
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UINT32 Buffer;
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UINT32 Buffer;
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if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
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return;
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}
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DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
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DEBUG ((EFI_D_INFO, "XhcSetBiosOwnership: called to set BIOS ownership\n"));
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Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
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Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
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@ -563,6 +567,10 @@ XhcClearBiosOwnership (
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{
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{
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UINT32 Buffer;
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UINT32 Buffer;
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if (Xhc->UsbLegSupOffset == 0xFFFFFFFF) {
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return;
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}
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DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
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DEBUG ((EFI_D_INFO, "XhcClearBiosOwnership: called to clear BIOS ownership\n"));
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Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
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Buffer = XhcReadExtCapReg (Xhc, Xhc->UsbLegSupOffset);
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@ -606,7 +614,7 @@ XhcGetCapabilityAddr (
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ExtCapOffset += (NextExtCapReg << 2);
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ExtCapOffset += (NextExtCapReg << 2);
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} while (NextExtCapReg != 0);
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} while (NextExtCapReg != 0);
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return 0;
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return 0xFFFFFFFF;
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}
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}
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/**
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/**
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@ -676,7 +684,7 @@ XhcResetHC (
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}
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}
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}
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}
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if (((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
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if ((Xhc->DebugCapSupOffset == 0xFFFFFFFF) || ((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset) & 0xFF) != XHC_CAP_USB_DEBUG) ||
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((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
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((XhcReadExtCapReg (Xhc, Xhc->DebugCapSupOffset + XHC_DC_DCCTRL) & BIT0) == 0)) {
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XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
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XhcSetOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET);
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Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
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Status = XhcWaitOpRegBit (Xhc, XHC_USBCMD_OFFSET, XHC_USBCMD_RESET, FALSE, Timeout);
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