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Revert "OvmfPkg/PlatformPei: hoist PciBase assignment above the i440fx/q35 branching"
This reverts commit 9a2e8d7c65ef7f39c6754d27e52954b616bc6628. The original fix for <https://bugzilla.tianocore.org/show_bug.cgi?id=1814> triggered a bug / incorrect assumption in QEMU. QEMU assumes that the PCIEXBAR is below the 32-bit PCI window, not above it. When the firmware doesn't satisfy this assumption, QEMU generates an \_SB.PCI0._CRS object in the ACPI DSDT that does not reflect the firmware's 32-bit MMIO BAR assignments. This causes OSes to re-assign 32-bit MMIO BARs. Working around the problem in the firmware looks less problematic than fixing QEMU. Revert the original changes first, before implementing an alternative fix. Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org> Cc: Gerd Hoffmann <kraxel@redhat.com> Cc: Jordan Justen <jordan.l.justen@intel.com> Ref: https://bugzilla.tianocore.org/show_bug.cgi?id=1859 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Philippe Mathieu-Daude <philmd@redhat.com> Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
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@ -181,7 +181,6 @@ MemMapInitialization (
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TopOfLowRam = GetSystemMemorySizeBelow4gb ();
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PciExBarBase = 0;
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PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
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if (mHostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {
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//
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// The MMCONFIG area is expected to fall between the top of low RAM and
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@ -193,6 +192,7 @@ MemMapInitialization (
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PciBase = (UINT32)(PciExBarBase + SIZE_256MB);
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PciSize = 0xFC000000 - PciBase;
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} else {
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PciBase = (TopOfLowRam < BASE_2GB) ? BASE_2GB : TopOfLowRam;
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PciSize = 0xFC000000 - PciBase;
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}
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