mirror of https://github.com/acidanthera/audk.git
Ring3: Added support for ARM User page table.
This commit is contained in:
Mikhail Krichanov
parent
d051ccdbe8
commit
75c5b9e27e
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@ -21,6 +21,16 @@
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#define ASM_FUNC(Name) _ASM_FUNC(ASM_PFX(Name), .text. ## Name)
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#define _ASM_FUNC_ALIGN(Name, Section, Align) \
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.global Name ; \
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.section #Section, "ax" ; \
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.type Name, %function ; \
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.balign Align ; \
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Name:
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#define ASM_FUNC_ALIGN(Name, Align) \
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_ASM_FUNC_ALIGN(ASM_PFX(Name), .text. ## Name, Align)
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#define MOV32(Reg, Val) \
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movw Reg, #(Val) & 0xffff ; \
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movt Reg, #(Val) >> 16
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@ -11,6 +11,7 @@
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#------------------------------------------------------------------------------
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#include <Library/PcdLib.h>
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#include <AsmMacroIoLib.h>
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/*
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@ -59,8 +60,10 @@ GCC_ASM_EXPORT(CommonCExceptionHandler)
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#if !defined(__APPLE__)
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.fpu neon @ makes vpush/vpop assemble
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#endif
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.align 5
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ASM_FUNC_ALIGN(ExceptionHandlerBase, 4096)
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.align 5
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//
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// This code gets copied to the ARM vector table
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@ -117,6 +120,8 @@ ASM_PFX(UndefinedInstructionEntry):
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bx R1
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ASM_PFX(SoftwareInterruptEntry):
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cpsid if
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isb
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srsdb #0x13! @ Store return state on SVC stack
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@ We are already in SVC mode
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stmfd SP!,{LR} @ Store the link register for the current mode
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@ -250,6 +255,24 @@ NoAdjustNeeded:
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vpush {d0-d15} @ save vstm registers in case they are used in optimizations
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#endif
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ldr R5, [SP, #0x40] @ Saved Processor Status Register
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and R5, R5, #0xF
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cmp R5, 0 @ Check whether EL0 process was interrupted
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bne NoTTBR0Switch
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mrc p15,0,R5,c2,c0,0 @ R5 == TTBR0
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ADRL (R6, UserPageTable)
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str R5, [R6]
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and R5, R5, #0x7F @ Preserve TTBR0 attributes
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LDRL (R6, ASM_PFX(CorePageTable))
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orr R6, R6, R5 @ Assign TTBR0 attributes
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mcr p15,0,R6,c2,c0,0 @ TTBR0 == R6
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mcr p15,0,r0,c8,c7,0 @ TLBIALL, TLB Invalidate All.
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mcr p15,0,r0,c7,c5,6 @ BPIALL, Branch Predictor Invalidate All.
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dsb
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isb
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NoTTBR0Switch:
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mov R4, SP @ Save current SP
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tst R4, #4
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subne SP, SP, #4 @ Adjust SP if not 8-byte aligned
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@ -269,6 +292,19 @@ CommonCExceptionHandler (
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mov SP, R4 @ Restore SP
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ldr R4, [SP, #0x40] @ Saved Processor Status Register
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and R4, R4, #0xF
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cmp R4, 0 @ Check whether EL0 process was interrupted
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bne NoTTBR0Switch2
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LDRL (R4, UserPageTable)
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mcr p15,0,R4,c2,c0,0 @ TTBR0 == R4
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mcr p15,0,r0,c8,c7,0 @ TLBIALL, TLB Invalidate All.
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mcr p15,0,r0,c7,c5,6 @ BPIALL, Branch Predictor Invalidate All.
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dsb
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isb
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NoTTBR0Switch2:
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#if (FixedPcdGet32(PcdVFPEnabled))
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vpop {d0-d15}
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#endif
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@ -290,3 +326,19 @@ CommonCExceptionHandler (
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add SP,SP,#0x20 @ Clear out the remaining stack space
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ldmfd SP!,{LR} @ restore the link register for this context
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rfefd SP! @ return from exception via srsfd stack slot
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ASM_FUNC_ALIGN(ExceptionHandlerFinal, 4096)
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.data
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.global ASM_PFX(CorePageTable)
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.balign 4096
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ASM_PFX(CorePageTable):
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.ds.l 1
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UserPageTable:
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.ds.l 1
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.balign 4096
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Padding:
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.ds.b 1
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@ -51,6 +51,7 @@ call:
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pop {R4-R8, LR}
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bx LR
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ASM_FUNC_ALIGN(SysCallBase, 4096)
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//------------------------------------------------------------------------------
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// EFI_STATUS
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// EFIAPI
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@ -63,13 +64,15 @@ call:
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// (r2) gRing3EntryPoint
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// (r3) gCoreSysCallStackTop
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//
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// (On Core Stack) &CoreSp
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// (On Core Stack) &CoreSp, gUserPageTable
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//------------------------------------------------------------------------------
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ASM_FUNC(ArmCallRing3)
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// Save registers.
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push {R4-R12, LR}
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// R6 is &CoreSp
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ldr R6, [SP, #0x28]
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// R7 is gUserPageTable
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ldr R7, [SP, #0x2C]
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#if (FixedPcdGet32(PcdVFPEnabled))
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// Save vstm registers in case they are used in optimizations.
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@ -94,10 +97,21 @@ ASM_FUNC(ArmCallRing3)
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str R5, [R6]
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mov SP, R3
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// Switch to UserPageTable.
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mrc p15,0,R8,c2,c0,0 // R8 == TTBR0
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and R8, R8, #0x7F // Preserve Core TTBR0 attributes.
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orr R7, R7, R8 // Assign Core attributes to UserPageTable.
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mcr p15,0,R7,c2,c0,0 // TTBR0 == UserPageTable
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mcr p15,0,r0,c8,c7,0 // TLBIALL, TLB Invalidate All.
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mcr p15,0,r0,c7,c5,6 // BPIALL, Branch Predictor Invalidate All.
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dsb
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isb
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push {R4}
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push {R2}
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rfefd SP
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ASM_FUNC_ALIGN(SysCallEnd, 4096)
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//------------------------------------------------------------------------------
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// VOID
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// EFIAPI
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@ -12,7 +12,7 @@
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#include "DxeMain.h"
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STATIC UINTN mCoreSp;
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extern UINTN gUartBaseAddress;
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UINTN gUserPageTable;
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EFI_STATUS
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EFIAPI
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@ -21,7 +21,8 @@ ArmCallRing3 (
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IN VOID *StackPointer,
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IN VOID *EntryPoint,
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IN VOID *SysCallStack,
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IN VOID *CoreStack
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IN VOID *CoreStack,
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IN UINTN UserPageTable
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);
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VOID
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@ -52,6 +53,8 @@ SysCallBootService (
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EFI_STATUS Status;
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EFI_PHYSICAL_ADDRESS Physical;
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ArmEnableInterrupts ();
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Status = CoreAllocatePages (
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AllocateAnyPages,
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EfiRing3MemoryType,
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@ -71,12 +74,6 @@ SysCallBootService (
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// All remaining arguments are on User Stack.
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//
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CopyMem ((VOID *)((UINTN)Physical + 5 * sizeof (UINTN)), (VOID *)UserRsp, 4 * sizeof (UINTN));
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SetUefiImageMemoryAttributes (
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gUartBaseAddress,
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EFI_PAGE_SIZE,
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EFI_MEMORY_XP
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);
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ForbidSupervisorAccessToUserMemory ();
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Status = CallBootService (
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@ -89,11 +86,7 @@ SysCallBootService (
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//
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CoreFreePages (Physical, EFI_SIZE_TO_PAGES (9 * sizeof (UINTN)));
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SetUefiImageMemoryAttributes (
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gUartBaseAddress,
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EFI_PAGE_SIZE,
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EFI_MEMORY_XP | EFI_MEMORY_USER
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);
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ArmDisableInterrupts ();
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return Status;
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}
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@ -141,6 +134,7 @@ InitializeMsr (
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}
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InitializeSysCallHandler (SysCallBootService);
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SetExceptionAddresses (NULL, 0);
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}
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VOID
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@ -171,5 +165,5 @@ CallRing3 (
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IN RING3_CALL_DATA *Data
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)
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{
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return ArmCallRing3 (Data, gRing3CallStackTop, gRing3EntryPoint, gCoreSysCallStackTop, &mCoreSp);
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return ArmCallRing3 (Data, gRing3CallStackTop, gRing3EntryPoint, gCoreSysCallStackTop, &mCoreSp, gUserPageTable);
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}
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