diff --git a/MdePkg/Library/BaseLib/BaseLib.inf b/MdePkg/Library/BaseLib/BaseLib.inf index 68b317f4e5..8838b9dc46 100644 --- a/MdePkg/Library/BaseLib/BaseLib.inf +++ b/MdePkg/Library/BaseLib/BaseLib.inf @@ -301,6 +301,7 @@ Ia32/MultU64x64.asm | INTEL Ia32/MultU64x32.nasm| INTEL Ia32/MultU64x32.asm | INTEL + Ia32/LShiftU64.nasm| INTEL Ia32/LShiftU64.asm | INTEL Ia32/LRotU64.asm | INTEL Ia32/LongJump.asm | INTEL @@ -366,6 +367,7 @@ Ia32/ARShiftU64.S | GCC Ia32/RShiftU64.nasm| GCC Ia32/RShiftU64.S | GCC + Ia32/LShiftU64.nasm| GCC Ia32/LShiftU64.S | GCC Ia32/EnableCache.S | GCC Ia32/DisableCache.S | GCC diff --git a/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm b/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm new file mode 100644 index 0000000000..239e6dfabe --- /dev/null +++ b/MdePkg/Library/BaseLib/Ia32/LShiftU64.nasm @@ -0,0 +1,45 @@ +;------------------------------------------------------------------------------ +; +; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.
+; This program and the accompanying materials +; are licensed and made available under the terms and conditions of the BSD License +; which accompanies this distribution. The full text of the license may be found at +; http://opensource.org/licenses/bsd-license.php. +; +; THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, +; WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. +; +; Module Name: +; +; LShiftU64.nasm +; +; Abstract: +; +; 64-bit left shift function for IA-32 +; +;------------------------------------------------------------------------------ + + SECTION .text + +;------------------------------------------------------------------------------ +; UINT64 +; EFIAPI +; InternalMathLShiftU64 ( +; IN UINT64 Operand, +; IN UINTN Count +; ); +;------------------------------------------------------------------------------ +global ASM_PFX(InternalMathLShiftU64) +ASM_PFX(InternalMathLShiftU64): + mov cl, [esp + 12] + xor eax, eax + mov edx, [esp + 4] + test cl, 32 ; Count >= 32? + jnz .0 + mov eax, edx + mov edx, [esp + 8] +.0: + shld edx, eax, cl + shl eax, cl + ret +