diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
index 0356abd7ab..93020e0b09 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/CpuExceptionCommon.h
@@ -40,7 +40,7 @@
 #include "ArchInterruptDefs.h"
 
 #define CPU_STACK_SWITCH_EXCEPTION_NUMBER \
-  FixedPcdGetSize (PcdCpuStackSwitchExceptionList)
+  (FixedPcdGetSize (PcdCpuStackSwitchExceptionList) + 1)
 
 #define CPU_STACK_SWITCH_EXCEPTION_LIST \
   FixedPcdGetPtr (PcdCpuStackSwitchExceptionList)
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
index 4b5898b33c..ae39125a1c 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/Ia32/ArchExceptionHandler.c
@@ -226,6 +226,7 @@ ArchSetupExceptionStack (
   StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
 
   Tss->ESP0             = StackTop;
+  StackTop             -= CPU_KNOWN_GOOD_STACK_SIZE;
   Tss->SS0              = AsmReadSs ();
   Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT);
   //
diff --git a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
index 7e61bb7e76..1b35108e97 100644
--- a/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
+++ b/UefiCpuPkg/Library/CpuExceptionHandlerLib/X64/ArchExceptionHandler.c
@@ -234,6 +234,7 @@ ArchSetupExceptionStack (
   StackTop = (UINTN)ALIGN_POINTER (StackTop, CPU_STACK_ALIGNMENT);
 
   Tss->RSP0             = StackTop;
+  StackTop             -= CPU_KNOWN_GOOD_STACK_SIZE;
   Tss->IOMapBaseAddress = sizeof (IA32_TASK_STATE_SEGMENT);
   //
   // Allow access to gUartBase = 0x3F8 and Offsets: 0x01, 0x03, 0x04, 0x05, 0x06;