mirror of https://github.com/acidanthera/audk.git
ArmPlatformPkg/ArmVExpressPkg: Create ArmVExpressPkg/Include/VExpressMotherBoard.h
This file contains the ARM Versatile Express motherboard definitions. It allows to avoid duplication between different platforms based on ARM VExpress motherboard. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@11749 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
6fd231c072
commit
76bc1743da
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@ -230,12 +230,14 @@
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NULL|ArmPkg/Library/CompilerIntrinsicsLib/CompilerIntrinsicsLib.inf
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[BuildOptions]
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RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A9 --thumb -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
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RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A9 -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
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RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
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RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A9 --thumb
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RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A9
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RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
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RVCT:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
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ARMGCC:*_*_ARM_ARCHCC_FLAGS == -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
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ARMGCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
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ARMGCC:*_*_ARM_ARCHCC_FLAGS ==
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ARMGCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
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ARMGCC:*_*_ARM_PLATFORM_FLAGS = -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include -I$(WORKSPACE)/ArmPlatformPkg/ArmVExpressPkg/Include/Platform/CTA9x4
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################################################################################
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@ -2,31 +2,34 @@
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* Header defining Versatile Express constants (Base addresses, sizes, flags)
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __ARM_VEXPRESS_H__
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#define __ARM_VEXPRESS_H__
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/*******************************************
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#include <Base.h>
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#include <VExpressMotherBoard.h>
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/***********************************************************************************
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// Platform Memory Map
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*******************************************/
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************************************************************************************/
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// Can be NOR0, NOR1, DRAM
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#define ARM_VE_REMAP_BASE 0x00000000
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#define ARM_VE_REMAP_SZ 0x04000000
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#define ARM_VE_REMAP_SZ SIZE_64MB
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// Motherboard Peripheral and On-chip peripheral
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#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_BASE 0x10000000
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#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ 0x10000000 /* 256 MB */
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#define ARM_VE_SMB_MB_ON_CHIP_PERIPH_SZ SIZE_256MB
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#define ARM_VE_BOARD_PERIPH_BASE 0x10000000
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#define ARM_VE_CHIP_PERIPH_BASE 0x10020000
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@ -36,17 +39,17 @@
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// NOR Flash 1
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#define ARM_VE_SMB_NOR0_BASE 0x40000000
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#define ARM_VE_SMB_NOR0_SZ 0x04000000 /* 64 MB */
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#define ARM_VE_SMB_NOR0_SZ SIZE_64MB
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// NOR Flash 2
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#define ARM_VE_SMB_NOR1_BASE 0x44000000
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#define ARM_VE_SMB_NOR1_SZ 0x04000000 /* 64 MB */
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#define ARM_VE_SMB_NOR1_SZ SIZE_64MB
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// SRAM
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#define ARM_VE_SMB_SRAM_BASE 0x48000000
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#define ARM_VE_SMB_SRAM_SZ 0x02000000 /* 32 MB */
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#define ARM_VE_SMB_SRAM_SZ SIZE_32MB
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// USB, Ethernet, VRAM
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#define ARM_VE_SMB_PERIPH_BASE 0x4C000000
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#define ARM_VE_SMB_PERIPH_VRAM 0x4C000000
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#define ARM_VE_SMB_PERIPH_SZ 0x04000000 /* 32 MB */
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#define PL111_CLCD_VRAM_MOTHERBOARD_BASE ARM_VE_SMB_PERIPH_BASE
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#define ARM_VE_SMB_PERIPH_SZ SIZE_64MB
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// DRAM
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#define ARM_VE_DRAM_BASE 0x60000000
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@ -54,49 +57,48 @@
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// External AXI between daughterboards (Logic Tile)
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#define ARM_VE_EXT_AXI_BASE 0xE0000000
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#define ARM_VE_EXT_AXI_SZ 0x20000000
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#define ARM_VE_EXT_AXI_SZ 0x20000000 /* 512 MB */
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/*******************************************
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// Motherboard peripherals
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*******************************************/
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// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
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#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
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#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
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#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
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#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
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#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
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#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
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#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
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/***********************************************************************************
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Core Tile memory-mapped Peripherals
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************************************************************************************/
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// SP810 Controller
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#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
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// PL111 Colour LCD Controller - core tile
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#define PL111_CLCD_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x20000)
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// Uart0
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#define PL011_CONSOLE_UART_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x09000)
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#define PL011_CONSOLE_UART_SPEED 38400
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// PL341 Dynamic Memory Controller Base
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#define ARM_VE_DMC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE0000)
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// SP804 Timer Bases
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#define SP804_TIMER0_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11000)
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#define SP804_TIMER1_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11020)
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#define SP804_TIMER2_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12000)
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#define SP804_TIMER3_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12020)
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// Dynamic Memory Controller Base
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#define ARM_VE_DMC_BASE 0x100E0000
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// Static Memory Controller Base
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#define ARM_VE_SMC_CTRL_BASE 0x100E1000
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// PL354 Static Memory Controller Base
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#define ARM_VE_SMC_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE1000)
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// System Configuration Controller register Base addresses
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//#define ARM_VE_SYS_CFG_CTRL_BASE 0x100E2000
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#define ARM_VE_SYS_CFGRW0_REG 0x100E2000
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#define ARM_VE_SYS_CFGRW1_REG 0x100E2004
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#define ARM_VE_SYS_CFGRW2_REG 0x100E2008
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//#define ARM_VE_SYS_CFG_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
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#define ARM_VE_SYS_CFGRW0_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2000)
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#define ARM_VE_SYS_CFGRW1_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2004)
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#define ARM_VE_SYS_CFGRW2_REG (ARM_VE_BOARD_PERIPH_BASE + 0xE2008)
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#define ARM_PLATFORM_SCC_BASE ARM_VE_SYS_CFGRW0_REG
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// SP805 Watchdog on Cortex A9 core tile
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#define SP805_WDOG_CORE_TILE_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE5000)
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// BP147 TZPC Base Address
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#define ARM_VE_TZPC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE6000)
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// PL301 Fast AXI Base Address
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#define ARM_VE_FAXI_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xE9000)
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// TZASC Trust Zone Address Space Controller Base Address
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#define ARM_VE_TZASC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0xEC000)
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// PL310 L2x0 Cache Controller Base Address
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//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000
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/***********************************************************************************
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Peripherals' misc settings
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************************************************************************************/
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#define ARM_VE_CFGRW1_TZASC_EN_BIT_MASK 0x2000
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#define ARM_VE_CFGRW1_REMAP_NOR0 0
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#define ARM_VE_CFGRW1_REMAP_EXT_AXI (1 << 29)
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#define ARM_VE_CFGRW1_REMAP_DRAM (1 << 30)
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// TZPC Base Address
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#define ARM_VE_TZPC_BASE 0x100E6000
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// PL301 Fast AXI Base Address
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#define ARM_VE_FAXI_BASE 0x100E9000
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// TZASC Defintions
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#define ARM_VE_TZASC_BASE 0x100EC000
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// TZASC - Other settings
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#define ARM_VE_DECPROT_BIT_TZPC (1 << 6)
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#define ARM_VE_DECPROT_BIT_DMC_TZASC (1 << 11)
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#define ARM_VE_DECPROT_BIT_NMC_TZASC (1 << 12)
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#define ARM_VE_DECPROT_BIT_NMC_TZASC_LOCK (1 << 4)
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#define ARM_VE_DECPROT_BIT_SMC_TZASC_LOCK (1 << 5)
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// L2x0 Cache Controller Base Address
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//#define ARM_VE_L2x0_CTLR_BASE 0x1E00A000
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/*******************************************
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/***********************************************************************************
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// Interrupt Map
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*******************************************/
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************************************************************************************/
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// Timer Interrupts
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#define TIMER01_INTERRUPT_NUM 34
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#define TIMER23_INTERRUPT_NUM 35
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#define TIMER01_INTERRUPT_NUM 34
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#define TIMER23_INTERRUPT_NUM 35
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/*******************************************
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/***********************************************************************************
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// EFI Memory Map in Permanent Memory (DRAM)
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*******************************************/
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************************************************************************************/
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// This region is allocated at the bottom of the DRAM. It will be used
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// for fixed address allocations such as Vector Table
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// This region is the memory declared to PEI as permanent memory for PEI
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// and DXE. EFI stacks and heaps will be declared in this region.
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#define ARM_VE_EFI_MEMORY_REGION_SZ 0x1000000
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#define ARM_VE_EFI_MEMORY_REGION_SZ SIZE_256MB
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#endif
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#endif
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@ -0,0 +1,76 @@
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/** @file
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* Header defining Versatile Express constants (Base addresses, sizes, flags)
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*
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* Copyright (c) 2011, ARM Limited. All rights reserved.
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*
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* This program and the accompanying materials
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* are licensed and made available under the terms and conditions of the BSD License
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* which accompanies this distribution. The full text of the license may be found at
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* http://opensource.org/licenses/bsd-license.php
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*
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* THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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* WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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*
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**/
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#ifndef __VEXPRESSMOTHERBOARD_H_
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#define __VEXPRESSMOTHERBOARD_H_
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#include <ArmPlatform.h>
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/***********************************************************************************
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// Motherboard memory-mapped peripherals
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************************************************************************************/
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// Define MotherBoard SYS flags offsets (from ARM_VE_BOARD_PERIPH_BASE)
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#define ARM_VE_SYS_LED_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00008)
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#define ARM_VE_SYS_FLAGS_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_VE_SYS_FLAGS_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00030)
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#define ARM_VE_SYS_FLAGS_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00034)
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#define ARM_VE_SYS_FLAGS_NV_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_VE_SYS_FLAGS_NV_SET_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00038)
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#define ARM_VE_SYS_FLAGS_NV_CLR_REG (ARM_VE_BOARD_PERIPH_BASE + 0x0003C)
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#define ARM_VE_SYS_FLASH (ARM_VE_BOARD_PERIPH_BASE + 0x0004C)
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#define ARM_VE_SYS_PROCID0_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00084)
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#define ARM_VE_SYS_PROCID1_REG (ARM_VE_BOARD_PERIPH_BASE + 0x00088)
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#define ARM_VE_SYS_CFGDATA_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A0)
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#define ARM_VE_SYS_CFGCTRL_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A4)
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#define ARM_VE_SYS_CFGSTAT_REG (ARM_VE_BOARD_PERIPH_BASE + 0x000A8)
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// SP810 Controller
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#define SP810_CTRL_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x01000)
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// Uart0
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#define PL011_CONSOLE_UART_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x09000)
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// SP805 Watchdog on motherboard
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#define SP805_WDOG_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x0F000)
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// SP804 Timer Bases
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#define SP804_TIMER0_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11000)
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#define SP804_TIMER1_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x11020)
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#define SP804_TIMER2_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12000)
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#define SP804_TIMER3_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x12020)
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// PL031 Real Time Clock
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#define PL031_RTC_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x17000)
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// PL111 Colour LCD Controller - motherboard
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#define PL111_CLCD_MOTHERBOARD_BASE (ARM_VE_BOARD_PERIPH_BASE + 0x1F000)
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#define PL111_CLCD_MOTHERBOARD_VIDEO_MODE_OSC_ID 1
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// VRAM offset for the PL111 Colour LCD Controller on the motherboard
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#define VRAM_MOTHERBOARD_BASE (ARM_VE_SMB_PERIPH_BASE + 0x00000)
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#define SYS_PROC_ID_UNSUPPORTED 0xFF
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#define SYS_PROC_ID_CORTEX_A9 0x0C
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//
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// Sites where the peripheral is fitted
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//
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#define ARM_VE_UNSUPPORTED ~0
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#define ARM_VE_MOTHERBOARD_SITE 0
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#define ARM_VE_DAUGHTERBOARD_1_SITE 1
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#define ARM_VE_DAUGHTERBOARD_2_SITE 2
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#endif /* VEXPRESSMOTHERBOARD_H_ */
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@ -67,7 +67,7 @@ ASM_PFX(ArmPlatformInitializeBootMemory):
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mov r5, lr
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// Initialize PL354 SMC
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LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
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LoadConstantToReg (ARM_VE_SMB_PERIPH_VRAM, r2)
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LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
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blx ASM_PFX(InitializeSMC)
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bx r5
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mov r5, lr
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// Initialize PL354 SMC
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LoadConstantToReg (ARM_VE_SMC_CTRL_BASE, r1)
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LoadConstantToReg (ARM_VE_SMB_PERIPH_VRAM, r2)
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LoadConstantToReg (VRAM_MOTHERBOARD_BASE, r2)
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blx InitializeSMC
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bx r5
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