mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg: RISC-V: MMU: Introduce a PCD for SATP mode
Introduce a PCD to control the maximum SATP mode that MMU allowed to use. This PCD helps RISC-V platform set bare or minimum SATP mode during bring up to debug memory map issue. Signed-off-by: Tuan Phan <tphan@ventanamicro.com> Reviewed-by: Dhaval Sharma <dhaval@rivosinc.com> Reviewed-by: Andrei Warkentin <andrei.warkentin@intel.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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@ -36,7 +36,7 @@
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#define PTE_PPN_SHIFT 10
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#define RISCV_MMU_PAGE_SHIFT 12
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STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39 };
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STATIC UINTN mModeSupport[] = { SATP_MODE_SV57, SATP_MODE_SV48, SATP_MODE_SV39, SATP_MODE_OFF };
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STATIC UINTN mMaxRootTableLevel;
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STATIC UINTN mBitPerLevel;
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STATIC UINTN mTableEntryCount;
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@ -590,6 +590,10 @@ RiscVMmuSetSatpMode (
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UINTN Index;
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EFI_STATUS Status;
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if (SatpMode > PcdGet32 (PcdCpuRiscVMmuMaxSatpMode)) {
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return EFI_DEVICE_ERROR;
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}
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switch (SatpMode) {
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case SATP_MODE_OFF:
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return EFI_SUCCESS;
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@ -25,3 +25,6 @@
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[LibraryClasses]
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BaseLib
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[Pcd]
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gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode ## CONSUMES
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@ -396,6 +396,14 @@
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# @Prompt Access to non-SMRAM memory is restricted to reserved, runtime and ACPI NVS type after SmmReadyToLock.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuSmmRestrictedMemoryAccess|TRUE|BOOLEAN|0x3213210F
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[PcdsFixedAtBuild.RISCV64]
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## Indicate the maximum SATP mode allowed.
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# 0 - Bare mode.
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# 8 - 39bit mode.
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# 9 - 48bit mode.
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# 10 - 57bit mode.
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gUefiCpuPkgTokenSpaceGuid.PcdCpuRiscVMmuMaxSatpMode|10|UINT32|0x60000021
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[PcdsDynamic, PcdsDynamicEx]
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## Contains the pointer to a CPU S3 data buffer of structure ACPI_CPU_DATA.
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# @Prompt The pointer to a CPU S3 data buffer.
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