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Cleanup Cache an MMU operations. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10348 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-04-07 18:13:58 +00:00
parent c5d00b30c1
commit 7800c283e0
2 changed files with 15 additions and 29 deletions
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19
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.S
View File

@ -41,6 +41,7 @@
.set IC_ON, (0x1<<12) .set IC_ON, (0x1<<12)
ASM_PFX(ArmInvalidateDataCacheEntryByMVA): ASM_PFX(ArmInvalidateDataCacheEntryByMVA):
mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line mcr p15, 0, r0, c7, c6, 1 @invalidate single data cache line
dsb dsb
@ -83,17 +84,8 @@ ASM_PFX(ArmCleanDataCacheEntryBySetWay):
bx lr bx lr
ASM_PFX(ArmDrainWriteBuffer):
mcr p15, 0, r0, c7, c10, 4 @ Drain write buffer for sync
dsb
isb
bx lr
ASM_PFX(ArmInvalidateInstructionCache): ASM_PFX(ArmInvalidateInstructionCache):
mov R0,#0
mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache mcr p15,0,R0,c7,c5,0 @Invalidate entire instruction cache
mov R0,#0
dsb dsb
isb isb
bx LR bx LR
@ -109,16 +101,15 @@ ASM_PFX(ArmEnableMmu):
ASM_PFX(ArmMmuEnabled): ASM_PFX(ArmMmuEnabled):
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
and R0,R0,#1 and R0,R0,#1
isb
bx LR bx LR
ASM_PFX(ArmDisableMmu): ASM_PFX(ArmDisableMmu):
mov R0,#0
mcr p15,0,R0,c13,c0,0 @FCSE PID register must be cleared before disabling MMU
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
bic R0,R0,#1 bic R0,R0,#1
mcr p15,0,R0,c1,c0,0 @Disable MMU mcr p15,0,R0,c1,c0,0 @Disable MMU
mcr p15,0,R0,c8,c7,0 @Invalidate TLB
mcr p15,0,R0,c7,c5,6 @Invalidate Branch predictor array
dsb dsb
isb isb
bx LR bx LR
@ -225,6 +216,7 @@ L_Skip:
bgt Loop1 bgt Loop1
L_Finished: L_Finished:
dsb
ldmfd SP!, {r4-r12, lr} ldmfd SP!, {r4-r12, lr}
bx LR bx LR
@ -233,6 +225,7 @@ ASM_PFX(ArmDataMemoryBarrier):
bx LR bx LR
ASM_PFX(ArmDataSyncronizationBarrier): ASM_PFX(ArmDataSyncronizationBarrier):
ASM_PFX(ArmDrainWriteBuffer):
dsb dsb
bx LR bx LR

25
ArmPkg/Library/ArmLib/ArmV7/ArmV7Support.asm
View File

@ -84,17 +84,8 @@ ArmCleanDataCacheEntryBySetWay
bx lr bx lr
ArmDrainWriteBuffer
mcr p15, 0, r0, c7, c10, 4 ; Drain write buffer for sync
dsb
isb
bx lr
ArmInvalidateInstructionCache ArmInvalidateInstructionCache
mov R0,#0
mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache mcr p15,0,R0,c7,c5,0 ;Invalidate entire instruction cache
mov R0,#0
dsb dsb
isb isb
bx LR bx LR
@ -110,15 +101,15 @@ ArmEnableMmu
ArmMmuEnabled ArmMmuEnabled
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
and R0,R0,#1 and R0,R0,#1
isb
bx LR bx LR
ArmDisableMmu ArmDisableMmu
mov R0,#0
mcr p15,0,R0,c13,c0,0 ;FCSE PID register must be cleared before disabling MMU
mrc p15,0,R0,c1,c0,0 mrc p15,0,R0,c1,c0,0
bic R0,R0,#1 bic R0,R0,#1
mcr p15,0,R0,c1,c0,0 ;Disable MMU mcr p15,0,R0,c1,c0,0 ;Disable MMU
mcr p15,0,R0,c8,c7,0 ;Invalidate TLB
mcr p15,0,R0,c7,c5,6 ;Invalidate Branch predictor array
dsb dsb
isb isb
bx LR bx LR
@ -127,7 +118,7 @@ ArmEnableDataCache
ldr R1,=DC_ON ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
orr R0,R0,R1 ;Set C bit orr R0,R0,R1 ;Set C bit
mcr p15,0,r0,c1,c0,0 ;Write control register configuration data mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
dsb dsb
isb isb
bx LR bx LR
@ -136,7 +127,7 @@ ArmDisableDataCache
ldr R1,=DC_ON ldr R1,=DC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
bic R0,R0,R1 ;Clear C bit bic R0,R0,R1 ;Clear C bit
mcr p15,0,r0,c1,c0,0 ;Write control register configuration data mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
isb isb
bx LR bx LR
@ -144,7 +135,7 @@ ArmEnableInstructionCache
ldr R1,=IC_ON ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
orr R0,R0,R1 ;Set I bit orr R0,R0,R1 ;Set I bit
mcr p15,0,r0,c1,c0,0 ;Write control register configuration data mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
dsb dsb
isb isb
bx LR bx LR
@ -153,7 +144,7 @@ ArmDisableInstructionCache
ldr R1,=IC_ON ldr R1,=IC_ON
mrc p15,0,R0,c1,c0,0 ;Read control register configuration data mrc p15,0,R0,c1,c0,0 ;Read control register configuration data
BIC R0,R0,R1 ;Clear I bit. BIC R0,R0,R1 ;Clear I bit.
mcr p15,0,r0,c1,c0,0 ;Write control register configuration data mcr p15,0,R0,c1,c0,0 ;Write control register configuration data
isb isb
bx LR bx LR
@ -217,6 +208,7 @@ Skip
bgt Loop1 bgt Loop1
Finished Finished
dsb
ldmfd SP!, {r4-r12, lr} ldmfd SP!, {r4-r12, lr}
bx LR bx LR
@ -226,6 +218,7 @@ ArmDataMemoryBarrier
bx LR bx LR
ArmDataSyncronizationBarrier ArmDataSyncronizationBarrier
ArmDrainWriteBuffer
dsb dsb
bx LR bx LR