tyler.durden/audk
1
0
Fork 0
mirror of https://github.com/acidanthera/audk.git synced 2025-04-08 17:05:09 +02:00
Code Issues Packages Projects Releases Wiki Activity

MdePkg Nvme.h: Update fields from 1.4c specification.

Browse Source 
Implement 1.4c specification update, specifically for
nvme sanitize capabilities.

Signed-off-by: Aaron Pop <aaronpop@microsoft.com>
This commit is contained in:
Ray Robles 2024-07-18 10:25:35 -07:00 committed by mergify[bot]
parent 1169122c6f
commit 7801fe428b
1 changed files with 53 additions and 23 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

76
MdePkg/Include/IndustryStandard/Nvme.h
View File

@ -3,6 +3,7 @@
(C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>
Copyright (c) 2017 - 2023, Intel Corporation. All rights reserved.<BR>
Copyright (c) Microsoft Corporation.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
@par Specification Reference:
@ -27,10 +28,12 @@
#define NVME_INTMC_OFFSET 0x0010 // Interrupt Mask Clear
#define NVME_CC_OFFSET 0x0014 // Controller Configuration
#define NVME_CSTS_OFFSET 0x001c // Controller Status
#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset
#define NVME_NSSR_OFFSET 0x0020 // NVM Subsystem Reset (Optional)
#define NVME_AQA_OFFSET 0x0024 // Admin Queue Attributes
#define NVME_ASQ_OFFSET 0x0028 // Admin Submission Queue Base Address
#define NVME_ACQ_OFFSET 0x0030 // Admin Completion Queue Base Address
#define NVME_CMBLOC_OFFSET 0x0038 // Control Memory Buffer Location (Optional)
#define NVME_CMBSZ_OFFSET 0x003C // Control Memory Buffer Size (Optional)
#define NVME_BPINFO_OFFSET 0x0040 // Boot Partition Information
#define NVME_BPRSEL_OFFSET 0x0044 // Boot Partition Read Select
#define NVME_BPMBL_OFFSET 0x0048 // Boot Partition Memory Buffer Location
@ -382,7 +385,21 @@ typedef struct {
UINT8 Cmic; /* Multi-interface Capabilities */
UINT8 Mdts; /* Maximum Data Transfer Size */
UINT8 Cntlid[2]; /* Controller ID */
UINT8 Rsvd1[176]; /* Reserved as of Nvm Express 1.1 Spec */
UINT32 Ver; /* Version */
UINT32 Rtd3r; /* RTD3 Resume Latency */
UINT32 Rtd3e; /* RTD3 Entry Latency */
UINT32 Oaes; /* Optional Async Events Supported */
UINT32 Ctratt; /* Controller Attributes */
UINT16 Rrls; /* Read Recovery Levels Supported */
UINT8 Rsvd1[9]; /* Reserved as of NVM Express 1.4c Spec */
UINT8 Cntrltype; /* Controller Type */
UINT8 Fguid[16]; /* FRU Globally Unique Identifier */
UINT16 Crdt1; /* Command Retry Delay Time 1 */
UINT16 Crdt2; /* Command Retry Delay Time 2 */
UINT16 Crdt3; /* Command Retry Delay Time 3 */
UINT8 Rsvd2[106]; /* Reserved as of NVM Express 1.4c Spec */
UINT8 Rsvd3[16]; /* Reserved for NVMe MI Spec */
//
// Admin Command Set Attributes
//
@ -418,30 +435,39 @@ typedef struct {
UINT16 Mntmt; /* Minimum Thermal Management Temperature */
UINT16 Mxtmt; /* Maximum Thermal Management Temperature */
NVME_SANICAP Sanicap; /* Sanitize Capabilities */
UINT8 Rsvd2[180]; /* Reserved as of Nvm Express 1.4 Spec */
UINT32 Hmminds; /* Host Memory Buffer Minimum Descriptor Entry Size */
UINT16 Hmmaxd; /* Host Memory Maximum Descriptors Entries */
UINT16 Nsetidmax; /* NVM Set Identifier Maximum */
UINT16 Endgidmax; /* Endurance Group Identifier Maximum */
UINT8 Anatt; /* ANA Transition Time */
UINT8 Anacap; /* Asymmetric Namespace Access Capabilities */
UINT32 Anagrpmax; /* ANA Group Identifier Maximum */
UINT32 Nanagrpid; /* Number of ANA Group Identifiers */
UINT32 Pels; /* Persistent Event Log Size */
UINT8 Rsvd4[156]; /* Reserved as of NVM Express 1.4c Spec */
//
// NVM Command Set Attributes
//
UINT8 Sqes; /* Submission Queue Entry Size */
UINT8 Cqes; /* Completion Queue Entry Size */
UINT16 Rsvd3; /* Reserved as of Nvm Express 1.1 Spec */
UINT32 Nn; /* Number of Namespaces */
UINT16 Oncs; /* Optional NVM Command Support */
UINT16 Fuses; /* Fused Operation Support */
UINT8 Fna; /* Format NVM Attributes */
UINT8 Vwc; /* Volatile Write Cache */
UINT16 Awun; /* Atomic Write Unit Normal */
UINT16 Awupf; /* Atomic Write Unit Power Fail */
UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
UINT8 Rsvd4; /* Reserved as of Nvm Express 1.1 Spec */
UINT16 Acwu; /* Atomic Compare & Write Unit */
UINT16 Rsvd5; /* Reserved as of Nvm Express 1.1 Spec */
UINT32 Sgls; /* SGL Support */
UINT8 Rsvd6[164]; /* Reserved as of Nvm Express 1.1 Spec */
//
// I/O Command set Attributes
//
UINT8 Rsvd7[1344]; /* Reserved as of Nvm Express 1.1 Spec */
UINT8 Sqes; /* Submission Queue Entry Size */
UINT8 Cqes; /* Completion Queue Entry Size */
UINT16 Maxcmd; /* Maximum Outstanding Commands */
UINT32 Nn; /* Number of Namespaces */
UINT16 Oncs; /* Optional NVM Command Support */
UINT16 Fuses; /* Fused Operation Support */
UINT8 Fna; /* Format NVM Attributes */
UINT8 Vwc; /* Volatile Write Cache */
UINT16 Awun; /* Atomic Write Unit Normal */
UINT16 Awupf; /* Atomic Write Unit Power Fail */
UINT8 Nvscc; /* NVM Vendor Specific Command Configuration */
UINT8 Nwpc; /* Namespace Write Protection Capabilities */
UINT16 Acwu; /* Atomic Compare & Write Unit */
UINT16 Rsvd5; /* Reserved as of NVM Express 1.4c Spec */
UINT32 Sgls; /* SGL Support */
UINT32 Mnan; /* Maximum Number of Allowed Namespace */
UINT8 Rsvd6[224]; /* Reserved as of NVM Express 1.4c Spec */
UINT8 Subnqn[256]; /* NVM Subsystem NVMe Qualified Name */
UINT8 Rsvd7[768]; /* Reserved as of NVM Express 1.4c Spec */
UINT8 Rsvd8[256]; /* Reserved for NVMe over Fabrics Spec */
//
// Power State Descriptors
//
@ -764,6 +790,10 @@ typedef struct {
UINT32 Rsvd1 : 20;
} NVME_ADMIN_FORMAT_NVM;
#define SES_NO_SECURE_ERASE 0x0
#define SES_USER_DATA_ERASE 0x1
#define SES_CRYPTO_ERASE 0x2
//
// NvmExpress Admin Security Receive Command
//