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ArmPlatformPkg: CodeQL Fixes.
Makes changes to comply with alerts raised by CodeQL. The issues here fall into the following category: 1. comparison-with-wider-type Signed-off-by: Eeshan Londhe <eeshanlondhe@microsoft.com>
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7327089f63
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79ad703b55
@ -140,10 +140,10 @@ VideoCopyHorizontalOverlap (
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UINT16 *SourcePixel16bit;
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UINT16 *SourcePixel16bit;
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UINT16 *DestinationPixel16bit;
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UINT16 *DestinationPixel16bit;
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UINT32 SourcePixelY;
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UINTN SourcePixelY;
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UINT32 DestinationPixelY;
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UINTN DestinationPixelY;
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UINTN SizeIn32Bits;
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UINTN SizeIn32Bits;
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UINTN SizeIn16Bits;
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UINTN SizeIn16Bits;
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Status = EFI_SUCCESS;
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Status = EFI_SUCCESS;
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@ -271,8 +271,8 @@ BltVideoFill (
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VOID *DestinationAddr;
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VOID *DestinationAddr;
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UINT16 *DestinationPixel16bit;
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UINT16 *DestinationPixel16bit;
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UINT16 Pixel16bit;
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UINT16 Pixel16bit;
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UINT32 DestinationPixelX;
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UINTN DestinationPixelX;
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UINT32 DestinationLine;
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UINTN DestinationLine;
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UINTN WidthInBytes;
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UINTN WidthInBytes;
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Status = EFI_SUCCESS;
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Status = EFI_SUCCESS;
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@ -420,11 +420,11 @@ BltVideoToBltBuffer (
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VOID *DestinationAddr;
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VOID *DestinationAddr;
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UINT16 *SourcePixel16bit;
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UINT16 *SourcePixel16bit;
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UINT16 Pixel16bit;
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UINT16 Pixel16bit;
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UINT32 SourcePixelX;
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UINTN SourcePixelX;
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UINT32 SourceLine;
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UINTN SourceLine;
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UINT32 DestinationPixelX;
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UINTN DestinationPixelX;
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UINT32 DestinationLine;
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UINTN DestinationLine;
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UINT32 BltBufferHorizontalResolution;
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UINTN BltBufferHorizontalResolution;
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UINTN WidthInBytes;
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UINTN WidthInBytes;
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Status = EFI_SUCCESS;
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Status = EFI_SUCCESS;
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@ -583,11 +583,11 @@ BltBufferToVideo (
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VOID *SourceAddr;
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VOID *SourceAddr;
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VOID *DestinationAddr;
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VOID *DestinationAddr;
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UINT16 *DestinationPixel16bit;
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UINT16 *DestinationPixel16bit;
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UINT32 SourcePixelX;
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UINTN SourcePixelX;
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UINT32 SourceLine;
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UINTN SourceLine;
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UINT32 DestinationPixelX;
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UINTN DestinationPixelX;
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UINT32 DestinationLine;
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UINTN DestinationLine;
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UINT32 BltBufferHorizontalResolution;
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UINTN BltBufferHorizontalResolution;
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UINTN WidthInBytes;
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UINTN WidthInBytes;
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Status = EFI_SUCCESS;
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Status = EFI_SUCCESS;
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@ -34,7 +34,7 @@ PL061Locate (
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OUT UINTN *RegisterBase
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OUT UINTN *RegisterBase
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)
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)
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{
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{
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UINT32 Index;
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UINTN Index;
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for (Index = 0; Index < mPL061PlatformGpio->GpioControllerCount; Index++) {
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for (Index = 0; Index < mPL061PlatformGpio->GpioControllerCount; Index++) {
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if ( (Gpio >= mPL061PlatformGpio->GpioController[Index].GpioIndex)
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if ( (Gpio >= mPL061PlatformGpio->GpioController[Index].GpioIndex)
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@ -74,18 +74,18 @@ UINTN
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EFIAPI
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EFIAPI
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PL061EffectiveAddress (
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PL061EffectiveAddress (
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IN UINTN Address,
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IN UINTN Address,
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IN UINTN Mask
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IN UINT8 Mask
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)
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)
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{
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{
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return ((Address + PL061_GPIO_DATA_REG_OFFSET) + (Mask << 2));
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return ((Address + PL061_GPIO_DATA_REG_OFFSET) + (UINTN)(Mask << 2));
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}
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}
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STATIC
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STATIC
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UINTN
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UINT8
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EFIAPI
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EFIAPI
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PL061GetPins (
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PL061GetPins (
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IN UINTN Address,
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IN UINTN Address,
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IN UINTN Mask
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IN UINT8 Mask
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)
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)
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{
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{
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return MmioRead8 (PL061EffectiveAddress (Address, Mask));
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return MmioRead8 (PL061EffectiveAddress (Address, Mask));
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@ -96,8 +96,8 @@ VOID
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EFIAPI
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EFIAPI
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PL061SetPins (
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PL061SetPins (
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IN UINTN Address,
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IN UINTN Address,
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IN UINTN Mask,
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IN UINT8 Mask,
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IN UINTN Value
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IN UINT8 Value
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)
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)
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{
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{
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MmioWrite8 (PL061EffectiveAddress (Address, Mask), Value);
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MmioWrite8 (PL061EffectiveAddress (Address, Mask), Value);
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@ -37,6 +37,6 @@
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#define PL061_GPIO_PINS 8
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#define PL061_GPIO_PINS 8
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// All bits low except one bit high, native bit length
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// All bits low except one bit high, native bit length
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#define GPIO_PIN_MASK(Pin) (1UL << ((UINTN)(Pin)))
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#define GPIO_PIN_MASK(Pin) (UINT8)(1 << (Pin & (PL061_GPIO_PINS - 1)))
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#endif // __PL061_GPIO_H__
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#endif // __PL061_GPIO_H__
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@ -24,7 +24,7 @@
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STATIC EFI_EVENT mEfiExitBootServicesEvent;
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STATIC EFI_EVENT mEfiExitBootServicesEvent;
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STATIC EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterrupt;
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STATIC EFI_HARDWARE_INTERRUPT_PROTOCOL *mInterrupt;
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STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
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STATIC EFI_WATCHDOG_TIMER_NOTIFY mWatchdogNotify;
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STATIC UINT32 mTimerPeriod;
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STATIC UINT64 mTimerPeriod;
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/**
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/**
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Make sure the SP805 registers are unlocked for writing.
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Make sure the SP805 registers are unlocked for writing.
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@ -101,7 +101,7 @@ SP805Stop (
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{
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{
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// Disable interrupts
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// Disable interrupts
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if ((MmioRead32 (SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) != 0) {
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if ((MmioRead32 (SP805_WDOG_CONTROL_REG) & SP805_WDOG_CTRL_INTEN) != 0) {
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MmioAnd32 (SP805_WDOG_CONTROL_REG, ~SP805_WDOG_CTRL_INTEN);
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MmioAnd32 (SP805_WDOG_CONTROL_REG, (UINT32) ~SP805_WDOG_CTRL_INTEN);
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}
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}
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}
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}
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@ -108,7 +108,7 @@
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#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
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#define PL111_CTRL_LCD_16BPP_565 (6 << 1)
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#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
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#define PL111_CTRL_LCD_12BPP_444 (7 << 1)
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#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
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#define PL111_CTRL_LCD_BPP(Bpp) ((Bpp) << 1)
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#define PL111_CTRL_LCD_EN 1
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#define PL111_CTRL_LCD_EN 1U
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/**********************************************************************/
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/**********************************************************************/
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