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IntelFsp2Pkg/GenCfgOpt.py: Coverity scan flags issues.

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REF: https://bugzilla.tianocore.org/show_bug.cgi?id=1706

Issue was: invalid_operation: Invalid operation on
null-like value "Base".
Fixed it by initializing Base to 0 before entering
while loop.

Test:
Compared script output before and after this patch and
the result is identical.

Cc: Maurice Ma <maurice.ma@intel.com>
Cc: Nate DeSimone <nathaniel.l.desimone@intel.com>
Cc: Star Zeng <star.zeng@intel.com>
Signed-off-by: Chasel Chiu <chasel.chiu@intel.com>
Reviewed-by: Star Zeng <star.zeng@intel.com>
Reviewed-by: Nate DeSimone <nathaniel.l.desimone@intel.com>
This commit is contained in:
Chasel Chiu 2020-02-07 16:33:36 +08:00 committed by mergify[bot]
parent a67efa3b22
commit 7a38ad07d0
1 changed files with 2 additions and 1 deletions
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3
IntelFsp2Pkg/Tools/GenCfgOpt.py
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@ -1,6 +1,6 @@
## @ GenCfgOpt.py ## @ GenCfgOpt.py
# #
# Copyright (c) 2014 - 2019, Intel Corporation. All rights reserved.<BR> # Copyright (c) 2014 - 2020, Intel Corporation. All rights reserved.<BR>
# SPDX-License-Identifier: BSD-2-Clause-Patent # SPDX-License-Identifier: BSD-2-Clause-Patent
# #
## ##
@ -439,6 +439,7 @@ EndList
MaxAlign = 32 #Default align to 32, but if there are 64 bit unit, align to 64 MaxAlign = 32 #Default align to 32, but if there are 64 bit unit, align to 64
SizeAlign = 0 #record the struct max align SizeAlign = 0 #record the struct max align
Base = 0 #Starting offset of sub-structure.
while len(DscLines): while len(DscLines):
DscLine = DscLines.pop(0).strip() DscLine = DscLines.pop(0).strip()
Handle = False Handle = False