mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/NvmExpressDxe: Fix some bugs
1) The Queue size field in create I/O submission/completion queue cmds is 0-based. the current code is 1-based. 2) a typo on allocated memory page size. it's inconsistent that some places is using 4 pages, but a place is using 6 pages. 3) a typo on PRP/SGL mechanism judgment. should directly use Psdt field rather than Opc field. 4) some platforms may not support UINT64 width access on MMIO register. Fix it to use two 32-bit width access. Signed-off-by: Feng Tian <feng.tian@intel.com> Reviewed-by: Kinney Michael <michael.d.kinney@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14657 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Feng Tian
erictian
parent
ad3f365641
commit
7b8883c6a9
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@ -214,6 +214,15 @@ EnumerateNvmeDevNamespace (
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EFI_OPEN_PROTOCOL_BY_CHILD_CONTROLLER
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);
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//
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// Dump NvmExpress Identify Namespace Data
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//
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DEBUG ((EFI_D_INFO, " == NVME IDENTIFY NAMESPACE [%d] DATA ==\n", NamespaceId));
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DEBUG ((EFI_D_INFO, " NSZE : 0x%x\n", NamespaceData->Nsze));
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DEBUG ((EFI_D_INFO, " NCAP : 0x%x\n", NamespaceData->Ncap));
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DEBUG ((EFI_D_INFO, " NUSE : 0x%x\n", NamespaceData->Nuse));
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DEBUG ((EFI_D_INFO, " LBAF0.LBADS : 0x%x\n", (NamespaceData->LbaFormat[0].Lbads)));
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//
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// Build controller name for Component Name (2) protocol.
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//
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@ -657,7 +666,7 @@ NvmExpressDriverBindingStart (
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PciIo,
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AllocateAnyPages,
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EfiBootServicesData,
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6,
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4,
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(VOID**)&Private->Buffer,
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0
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);
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@ -56,11 +56,11 @@ extern EFI_DRIVER_SUPPORTED_EFI_VERSION_PROTOCOL gNvmExpressDriverSupportedEfiV
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#define PCI_CLASS_MASS_STORAGE_NVM 0x08 // mass storage sub-class non-volatile memory.
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#define PCI_IF_NVMHCI 0x02 // mass storage programming interface NVMHCI.
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#define NVME_ASQ_SIZE 2 // Number of admin submission queue entries
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#define NVME_ACQ_SIZE 2 // Number of admin completion queue entries
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#define NVME_ASQ_SIZE 1 // Number of admin submission queue entries, which is 0-based
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#define NVME_ACQ_SIZE 1 // Number of admin completion queue entries, which is 0-based
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#define NVME_CSQ_SIZE 2 // Number of I/O submission queue entries
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#define NVME_CCQ_SIZE 2 // Number of I/O completion queue entries
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#define NVME_CSQ_SIZE 1 // Number of I/O submission queue entries, which is 0-based
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#define NVME_CCQ_SIZE 1 // Number of I/O completion queue entries, which is 0-based
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#define NVME_MAX_IO_QUEUES 2 // Number of I/O queues supported by the driver
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@ -172,10 +172,12 @@ NvmeRead (
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UINT32 BlockSize;
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NVME_CONTROLLER_PRIVATE_DATA *Controller;
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UINT32 MaxTransferBlocks;
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UINTN OrginalBlocks;
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Status = EFI_SUCCESS;
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Controller = Device->Controller;
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BlockSize = Device->Media.BlockSize;
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Status = EFI_SUCCESS;
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Controller = Device->Controller;
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BlockSize = Device->Media.BlockSize;
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OrginalBlocks = Blocks;
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if (Controller->ControllerData->Mdts != 0) {
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MaxTransferBlocks = (1 << (Controller->ControllerData->Mdts)) * (1 << (Controller->Cap.Mpsmin + 12)) / BlockSize;
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@ -200,7 +202,7 @@ NvmeRead (
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}
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}
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DEBUG ((EFI_D_INFO, "NvmeRead() Lba = %8d, Blocks = %8d, BlockSize = %d Status = %r\n", Lba, Blocks, BlockSize, Status));
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DEBUG ((EFI_D_INFO, "NvmeRead() Lba = 0x%08x, Original = 0x%08x, Remaining = 0x%08x, BlockSize = 0x%x Status = %r\n", Lba, OrginalBlocks, Blocks, BlockSize, Status));
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return Status;
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}
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@ -229,10 +231,12 @@ NvmeWrite (
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UINT32 BlockSize;
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NVME_CONTROLLER_PRIVATE_DATA *Controller;
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UINT32 MaxTransferBlocks;
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UINTN OrginalBlocks;
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Status = EFI_SUCCESS;
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Controller = Device->Controller;
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BlockSize = Device->Media.BlockSize;
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Status = EFI_SUCCESS;
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Controller = Device->Controller;
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BlockSize = Device->Media.BlockSize;
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OrginalBlocks = Blocks;
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if (Controller->ControllerData->Mdts != 0) {
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MaxTransferBlocks = (1 << (Controller->ControllerData->Mdts)) * (1 << (Controller->Cap.Mpsmin + 12)) / BlockSize;
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@ -257,7 +261,7 @@ NvmeWrite (
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}
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}
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DEBUG ((EFI_D_INFO, "NvmeWrite() Lba = %8d, Blocks = %8d, BlockSize = %d Status = %r\n", Lba, Blocks, BlockSize, Status));
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DEBUG ((EFI_D_INFO, "NvmeWrite() Lba = 0x%08x, Original = 0x%08x, Remaining = 0x%08x, BlockSize = 0x%x Status = %r\n", Lba, OrginalBlocks, Blocks, BlockSize, Status));
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return Status;
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}
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@ -33,21 +33,23 @@ ReadNvmeControllerCapabilities (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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PciIo = Private->PciIo;
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint64,
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EfiPciIoWidthUint32,
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NVME_BAR,
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NVME_CAP_OFFSET,
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1,
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Cap
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2,
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&Data
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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WriteUnaligned64 ((UINT64*)Cap, Data);
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return EFI_SUCCESS;
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}
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@ -69,6 +71,7 @@ ReadNvmeControllerConfiguration (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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PciIo = Private->PciIo;
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Status = PciIo->Mem.Read (
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@ -77,13 +80,14 @@ ReadNvmeControllerConfiguration (
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NVME_BAR,
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NVME_CC_OFFSET,
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1,
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Cc
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&Data
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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WriteUnaligned32 ((UINT32*)Cc, Data);
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return EFI_SUCCESS;
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}
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@ -105,15 +109,17 @@ WriteNvmeControllerConfiguration (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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PciIo = Private->PciIo;
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Data = ReadUnaligned32 ((UINT32*)Cc);
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Status = PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint32,
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NVME_BAR,
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NVME_CC_OFFSET,
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1,
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Cc
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&Data
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);
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if (EFI_ERROR(Status)) {
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@ -149,6 +155,7 @@ ReadNvmeControllerStatus (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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PciIo = Private->PciIo;
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Status = PciIo->Mem.Read (
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@ -157,13 +164,14 @@ ReadNvmeControllerStatus (
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NVME_BAR,
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NVME_CSTS_OFFSET,
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1,
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Csts
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&Data
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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WriteUnaligned32 ((UINT32*)Csts, Data);
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return EFI_SUCCESS;
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}
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@ -185,6 +193,7 @@ ReadNvmeAdminQueueAttributes (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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PciIo = Private->PciIo;
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Status = PciIo->Mem.Read (
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@ -193,13 +202,14 @@ ReadNvmeAdminQueueAttributes (
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NVME_BAR,
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NVME_AQA_OFFSET,
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1,
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Aqa
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&Data
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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WriteUnaligned32 ((UINT32*)Aqa, Data);
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return EFI_SUCCESS;
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}
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@ -221,15 +231,17 @@ WriteNvmeAdminQueueAttributes (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT32 Data;
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PciIo = Private->PciIo;
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Data = ReadUnaligned32 ((UINT32*)Aqa);
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Status = PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint32,
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NVME_BAR,
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NVME_AQA_OFFSET,
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1,
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Aqa
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&Data
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);
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if (EFI_ERROR(Status)) {
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@ -260,21 +272,23 @@ ReadNvmeAdminSubmissionQueueBaseAddress (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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PciIo = Private->PciIo;
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint64,
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EfiPciIoWidthUint32,
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NVME_BAR,
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NVME_ASQ_OFFSET,
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1,
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Asq
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2,
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&Data
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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WriteUnaligned64 ((UINT64*)Asq, Data);
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return EFI_SUCCESS;
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}
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@ -296,15 +310,18 @@ WriteNvmeAdminSubmissionQueueBaseAddress (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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PciIo = Private->PciIo;
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Data = ReadUnaligned64 ((UINT64*)Asq);
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Status = PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint64,
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EfiPciIoWidthUint32,
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NVME_BAR,
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NVME_ASQ_OFFSET,
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1,
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Asq
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2,
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&Data
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);
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if (EFI_ERROR(Status)) {
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@ -334,21 +351,24 @@ ReadNvmeAdminCompletionQueueBaseAddress (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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PciIo = Private->PciIo;
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Status = PciIo->Mem.Read (
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PciIo,
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EfiPciIoWidthUint64,
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EfiPciIoWidthUint32,
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NVME_BAR,
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NVME_ACQ_OFFSET,
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1,
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Acq
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2,
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&Data
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);
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if (EFI_ERROR(Status)) {
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return Status;
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}
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WriteUnaligned64 ((UINT64*)Acq, Data);
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return EFI_SUCCESS;
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}
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@ -370,15 +390,18 @@ WriteNvmeAdminCompletionQueueBaseAddress (
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{
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EFI_PCI_IO_PROTOCOL *PciIo;
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EFI_STATUS Status;
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UINT64 Data;
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PciIo = Private->PciIo;
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Data = ReadUnaligned64 ((UINT64*)Acq);
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Status = PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint64,
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EfiPciIoWidthUint32,
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NVME_BAR,
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NVME_ACQ_OFFSET,
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1,
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Acq
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2,
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&Data
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);
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if (EFI_ERROR(Status)) {
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@ -921,6 +944,25 @@ NvmeControllerInit (
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Private->ControllerData = NULL;
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return EFI_NOT_FOUND;
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}
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//
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// Dump NvmExpress Identify Controller Data
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//
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Private->ControllerData->Sn[19] = 0;
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Private->ControllerData->Mn[39] = 0;
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DEBUG ((EFI_D_INFO, " == NVME IDENTIFY CONTROLLER DATA ==\n"));
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DEBUG ((EFI_D_INFO, " PCI VID : 0x%x\n", Private->ControllerData->Vid));
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DEBUG ((EFI_D_INFO, " PCI SSVID : 0x%x\n", Private->ControllerData->Ssvid));
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DEBUG ((EFI_D_INFO, " SN : %a\n", (CHAR8 *)(Private->ControllerData->Sn)));
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DEBUG ((EFI_D_INFO, " MN : %a\n", (CHAR8 *)(Private->ControllerData->Mn)));
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DEBUG ((EFI_D_INFO, " FR : 0x%x\n", *((UINT64*)Private->ControllerData->Fr)));
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DEBUG ((EFI_D_INFO, " RAB : 0x%x\n", Private->ControllerData->Rab));
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DEBUG ((EFI_D_INFO, " IEEE : 0x%x\n", *(UINT32*)Private->ControllerData->Ieee_oiu));
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DEBUG ((EFI_D_INFO, " AERL : 0x%x\n", Private->ControllerData->Aerl));
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DEBUG ((EFI_D_INFO, " SQES : 0x%x\n", Private->ControllerData->Sqes));
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DEBUG ((EFI_D_INFO, " CQES : 0x%x\n", Private->ControllerData->Cqes));
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DEBUG ((EFI_D_INFO, " NN : 0x%x\n", Private->ControllerData->Nn));
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return Status;
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}
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@ -387,6 +387,7 @@ NvmExpressPassThru (
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UINT64 *Prp;
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VOID *PrpListHost;
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UINTN PrpListNo;
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UINT32 Data;
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//
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// check the data fields in Packet parameter.
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@ -431,8 +432,8 @@ NvmExpressPassThru (
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//
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// Currently we only support PRP for data transfer, SGL is NOT supported.
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//
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ASSERT ((Sq->Opc & BIT15) == 0);
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if ((Sq->Opc & BIT15) != 0) {
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ASSERT (Sq->Psdt == 0);
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if (Sq->Psdt != 0) {
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DEBUG ((EFI_D_ERROR, "NvmExpressPassThru: doesn't support SGL mechanism\n"));
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return EFI_UNSUPPORTED;
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}
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@ -534,14 +535,14 @@ NvmExpressPassThru (
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// Ring the submission queue doorbell.
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//
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Private->SqTdbl[Qid].Sqt ^= 1;
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Data = ReadUnaligned32 ((UINT32*)&Private->SqTdbl[Qid]);
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PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint32,
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NVME_BAR,
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NVME_SQTDBL_OFFSET(Qid, Private->Cap.Dstrd),
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1,
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&Private->SqTdbl[Qid]
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&Data
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);
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Status = gBS->CreateEvent (
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@ -591,13 +592,14 @@ NvmExpressPassThru (
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NvmeDumpStatus(Cq);
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DEBUG_CODE_END();
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Data = ReadUnaligned32 ((UINT32*)&Private->CqHdbl[Qid]);
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PciIo->Mem.Write (
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PciIo,
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EfiPciIoWidthUint32,
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NVME_BAR,
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NVME_CQHDBL_OFFSET(Qid, Private->Cap.Dstrd),
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1,
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&Private->CqHdbl[Qid]
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&Data
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);
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EXIT:
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