mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg: Change complex DEBUG_CODE() to DEBUG_CODE_BEGIN/END()
REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3767 Update use of DEBUG_CODE(Expression) if Expression is a complex code block with if/while/for/case statements that use {}. Cc: Andrew Fish <afish@apple.com> Cc: Leif Lindholm <leif@nuviainc.com> Cc: Michael Kubacki <michael.kubacki@microsoft.com> Signed-off-by: Michael D Kinney <michael.d.kinney@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com>
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@ -1071,7 +1071,7 @@ AddMemoryMappedIoSpace (
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}
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}
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DEBUG_CODE (
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DEBUG_CODE_BEGIN ();
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//
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// Make sure there are adjacent descriptors covering [Base, Base + Length).
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// It is possible that they have not been merged; merging can be prevented
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@ -1089,7 +1089,7 @@ AddMemoryMappedIoSpace (
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ASSERT (Descriptor.GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo);
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ASSERT ((Descriptor.Capabilities & Capabilities) == Capabilities);
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}
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);
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DEBUG_CODE_END ();
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FreeMemorySpaceMap:
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FreePool (MemorySpaceMap);
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@ -1212,4 +1212,3 @@ InitializeCpu (
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return Status;
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}
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@ -243,7 +243,7 @@ GetApicMode (
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VOID
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)
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{
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DEBUG_CODE (
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DEBUG_CODE_BEGIN ();
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{
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MSR_IA32_APIC_BASE_REGISTER ApicBaseMsr;
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@ -259,7 +259,7 @@ GetApicMode (
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ASSERT (ApicBaseMsr.Bits.EXTD == 0);
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}
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}
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);
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DEBUG_CODE_END ();
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return LOCAL_APIC_MODE_XAPIC;
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}
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@ -2155,7 +2155,7 @@ MpInitLibInitialize (
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//
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// Dump the microcode revision for each core.
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//
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DEBUG_CODE (
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DEBUG_CODE_BEGIN ();
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UINT32 ThreadId;
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UINT32 ExpectedMicrocodeRevision;
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CpuInfoInHob = (CPU_INFO_IN_HOB *) (UINTN) CpuMpData->CpuInfoInHob;
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@ -2176,7 +2176,7 @@ MpInitLibInitialize (
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));
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}
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}
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);
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DEBUG_CODE_END ();
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//
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// Initialize global data for MP support
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//
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@ -2186,7 +2186,7 @@ MtrrSetMemoryAttributesInMtrrSettings (
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//
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// 0. Dump the requests.
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//
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DEBUG_CODE (
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DEBUG_CODE_BEGIN ();
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DEBUG ((DEBUG_CACHE, "Mtrr: Set Mem Attribute to %a, ScratchSize = %x%a",
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(MtrrSetting == NULL) ? "Hardware" : "Buffer", *ScratchSize,
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(RangeCount <= 1) ? "," : "\n"
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@ -2197,7 +2197,7 @@ MtrrSetMemoryAttributesInMtrrSettings (
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Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length
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));
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}
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);
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DEBUG_CODE_END ();
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//
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// 1. Validate the parameters.
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@ -2715,7 +2715,7 @@ MtrrDebugPrintAllMtrrsWorker (
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IN MTRR_SETTINGS *MtrrSetting
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)
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{
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DEBUG_CODE (
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DEBUG_CODE_BEGIN ();
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MTRR_SETTINGS LocalMtrrs;
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MTRR_SETTINGS *Mtrrs;
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UINTN Index;
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@ -2799,7 +2799,7 @@ MtrrDebugPrintAllMtrrsWorker (
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Ranges[Index].BaseAddress, Ranges[Index].BaseAddress + Ranges[Index].Length - 1
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));
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}
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);
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DEBUG_CODE_END ();
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}
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/**
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@ -636,7 +636,7 @@ AnalysisProcessorFeatures (
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//
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// Dump the last CPU feature list
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//
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DEBUG_CODE (
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DEBUG_CODE_BEGIN ();
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DEBUG ((DEBUG_INFO, "Last CPU features list...\n"));
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Entry = GetFirstNode (&CpuFeaturesData->FeatureList);
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while (!IsNull (&CpuFeaturesData->FeatureList, Entry)) {
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@ -659,7 +659,7 @@ AnalysisProcessorFeatures (
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DumpCpuFeatureMask (PcdGetPtr (PcdCpuFeaturesSetting), CpuFeaturesData->BitMaskSize);
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DEBUG ((DEBUG_INFO, "Final PcdCpuFeaturesSetting:\n"));
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DumpCpuFeatureMask (CpuFeaturesData->SettingPcd, CpuFeaturesData->BitMaskSize);
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);
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DEBUG_CODE_END ();
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//
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// Save PCDs and display CPU PCDs
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@ -1190,4 +1190,3 @@ CpuFeaturesDetect (
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AnalysisProcessorFeatures (CpuFeaturesData->NumberOfCpus);
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}
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@ -597,12 +597,12 @@ PiCpuSmmEntry (
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// If support CPU hot plug, PcdCpuSmmEnableBspElection should be set to TRUE.
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// A constant BSP index makes no sense because it may be hot removed.
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//
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DEBUG_CODE (
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DEBUG_CODE_BEGIN ();
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if (FeaturePcdGet (PcdCpuHotPlugSupport)) {
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ASSERT (FeaturePcdGet (PcdCpuSmmEnableBspElection));
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}
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);
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DEBUG_CODE_END ();
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//
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// Save the PcdCpuSmmCodeAccessCheckEnable value into a global variable.
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