mirror of https://github.com/acidanthera/audk.git
OvmfPkg: sync FADT with QEMU: correct SMI_CMD
- Qemu's PIIX emulation actually supports SMM and ACPI_ENABLE / ACPI_DISABLE. - After enabling SMI_CMD (SMI_CMD_IO_PORT), further values to be written there must be synchronized with qemu: PSTATE_CNT, CST_CNT. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Jordan Justen <jordan.l.justen@intel.com> git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13611 6f19259b-4bc3-4df7-8a09-765794883524
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@ -33,7 +33,7 @@ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
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ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
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ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
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S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
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0xE2, // PState control
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0, // PState control
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PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk
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PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk
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PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk
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@ -49,7 +49,7 @@ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
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GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
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GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
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GPE1_BASE, // offset in gpe model where gpe1 events start
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0xE3, // _CST support
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0, // _CST support
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P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
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P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
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FLUSH_SIZE, // Size of area read to flush caches
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@ -29,9 +29,9 @@
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#define INT_MODEL 0x01
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#define SCI_INT_VECTOR 0x0009
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#define SMI_CMD_IO_PORT 0 // If SMM was supported, then this would be 0xB2
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#define ACPI_ENABLE 0
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#define ACPI_DISABLE 0
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#define SMI_CMD_IO_PORT 0xB2
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#define ACPI_ENABLE 0xF1
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#define ACPI_DISABLE 0xF0
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#define S4BIOS_REQ 0x00
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#define PM1a_EVT_BLK 0x0000b000
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#define PM1b_EVT_BLK 0x00000000
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