OvmfPkg: sync FADT with QEMU: correct SMI_CMD

- Qemu's PIIX emulation actually supports SMM and ACPI_ENABLE /
  ACPI_DISABLE.

- After enabling SMI_CMD (SMI_CMD_IO_PORT), further values to be written
  there must be synchronized with qemu: PSTATE_CNT, CST_CNT.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@13611 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
jljusten 2012-08-13 15:38:16 +00:00
parent 2712ab4f54
commit 7c9ff57b11
2 changed files with 5 additions and 5 deletions

View File

@ -33,7 +33,7 @@ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI
ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI
S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state
0xE2, // PState control
0, // PState control
PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk
PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk
PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk
@ -49,7 +49,7 @@ EFI_ACPI_1_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {
GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk
GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk
GPE1_BASE, // offset in gpe model where gpe1 events start
0xE3, // _CST support
0, // _CST support
P_LVL2_LAT, // worst case HW latency to enter/exit C2 state
P_LVL3_LAT, // worst case HW latency to enter/exit C3 state
FLUSH_SIZE, // Size of area read to flush caches

View File

@ -29,9 +29,9 @@
#define INT_MODEL 0x01
#define SCI_INT_VECTOR 0x0009
#define SMI_CMD_IO_PORT 0 // If SMM was supported, then this would be 0xB2
#define ACPI_ENABLE 0
#define ACPI_DISABLE 0
#define SMI_CMD_IO_PORT 0xB2
#define ACPI_ENABLE 0xF1
#define ACPI_DISABLE 0xF0
#define S4BIOS_REQ 0x00
#define PM1a_EVT_BLK 0x0000b000
#define PM1b_EVT_BLK 0x00000000