From 7e119c677efc857a603b10ffc632ddfd5cd31b54 Mon Sep 17 00:00:00 2001 From: Olivier Martin Date: Tue, 29 Jul 2014 14:06:33 +0000 Subject: [PATCH] ArmPkg/AArch64.h: Added SPSR and Timer register definitions These timer register definitions are AArch64 specific. It is the reason why they are into this file and not into Chipset/ArmArchTimer.h. Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Olivier Martin git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15706 6f19259b-4bc3-4df7-8a09-765794883524 --- ArmPkg/Include/Chipset/AArch64.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/ArmPkg/Include/Chipset/AArch64.h b/ArmPkg/Include/Chipset/AArch64.h index 72bde15afe..9c3727002e 100644 --- a/ArmPkg/Include/Chipset/AArch64.h +++ b/ArmPkg/Include/Chipset/AArch64.h @@ -66,6 +66,25 @@ #define AARCH64_EL2 0x8 #define AARCH64_EL1 0x4 +// Saved Program Status Register definitions +#define SPSR_A BIT8 +#define SPSR_I BIT7 +#define SPSR_F BIT6 + +#define SPSR_AARCH32 BIT4 + +#define SPSR_AARCH32_MODE_USER 0x0 +#define SPSR_AARCH32_MODE_FIQ 0x1 +#define SPSR_AARCH32_MODE_IRQ 0x2 +#define SPSR_AARCH32_MODE_SVC 0x3 +#define SPSR_AARCH32_MODE_ABORT 0x7 +#define SPSR_AARCH32_MODE_UNDEF 0xB +#define SPSR_AARCH32_MODE_SYS 0xF + +// Counter-timer Hypervisor Control register definitions +#define CNTHCTL_EL2_EL1PCTEN BIT0 +#define CNTHCTL_EL2_EL1PCEN BIT1 + #define ARM_VECTOR_TABLE_ALIGNMENT ((1 << 11)-1) VOID