mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/PiSmmCpu: Change variable names and comments to follow SDM
Per SDM, for IA-32e 4-KByte paging, there are four layers in the page table structure: 1. PML4 2. Page-Directory-Pointer Table (PDPT) 3. Page-Directory (PD) 4. Page Table (PT) The patch changes the local variable names and comments to use "PML4", "PDPT", "PD", "PT" to better align to terms used in SDM. There is no functionality impact for this change. Signed-off-by: Ray Ni <ray.ni@intel.com> Cc: Eric Dong <eric.dong@intel.com> Regression-tested-by: Laszlo Ersek <lersek@redhat.com> Reviewed-by: Eric Dong <eric.dong@intel.com>
This commit is contained in:
Ray Ni
parent
034a3b4f55
commit
7e56f8928d
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@ -535,15 +535,15 @@ InitPaging (
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)
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{
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UINT64 *Pml4;
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UINT64 *Pde;
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UINT64 *Pte;
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UINT64 *Pdpt;
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UINT64 *Pd;
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UINT64 *Pt;
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UINTN Address;
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UINTN Level1;
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UINTN Level2;
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UINTN Level3;
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UINTN Level4;
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UINTN NumberOfPdpEntries;
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UINTN Pml4Index;
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UINTN PdptIndex;
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UINTN PdIndex;
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UINTN PtIndex;
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UINTN NumberOfPdptEntries;
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UINTN NumberOfPml4Entries;
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UINTN SizeOfMemorySpace;
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BOOLEAN Nx;
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@ -556,143 +556,143 @@ InitPaging (
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//
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if (SizeOfMemorySpace <= 39 ) {
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NumberOfPml4Entries = 1;
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NumberOfPdpEntries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 30));
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NumberOfPdptEntries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 30));
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} else {
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NumberOfPml4Entries = (UINT32)LShiftU64 (1, (SizeOfMemorySpace - 39));
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NumberOfPdpEntries = 512;
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NumberOfPdptEntries = 512;
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}
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} else {
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NumberOfPml4Entries = 1;
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NumberOfPdpEntries = 4;
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NumberOfPdptEntries = 4;
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}
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//
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// Go through page table and change 2MB-page into 4KB-page.
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//
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for (Level1 = 0; Level1 < NumberOfPml4Entries; Level1++) {
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for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
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if (sizeof (UINTN) == sizeof (UINT64)) {
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if ((Pml4[Level1] & IA32_PG_P) == 0) {
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if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
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//
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// If Pml4 entry does not exist, skip it
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// If PML4 entry does not exist, skip it
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//
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continue;
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}
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Pde = (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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} else {
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Pde = (UINT64*)(UINTN)mSmmProfileCr3;
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Pdpt = (UINT64*)(UINTN)mSmmProfileCr3;
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}
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for (Level2 = 0; Level2 < NumberOfPdpEntries; Level2++, Pde++) {
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if ((*Pde & IA32_PG_P) == 0) {
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for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
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if ((*Pdpt & IA32_PG_P) == 0) {
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//
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// If PDE entry does not exist, skip it
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// If PDPT entry does not exist, skip it
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//
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continue;
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}
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if ((*Pde & IA32_PG_PS) != 0) {
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if ((*Pdpt & IA32_PG_PS) != 0) {
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//
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// This is 1G entry, skip it
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//
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continue;
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}
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Pte = (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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if (Pte == 0) {
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Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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if (Pd == 0) {
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continue;
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}
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for (Level3 = 0; Level3 < SIZE_4KB / sizeof (*Pte); Level3++, Pte++) {
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if ((*Pte & IA32_PG_P) == 0) {
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for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {
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if ((*Pd & IA32_PG_P) == 0) {
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//
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// If PTE entry does not exist, skip it
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// If PD entry does not exist, skip it
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//
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continue;
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}
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Address = (((Level2 << 9) + Level3) << 21);
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Address = (((PdptIndex << 9) + PdIndex) << 21);
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//
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// If it is 2M page, check IsAddressSplit()
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//
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if (((*Pte & IA32_PG_PS) != 0) && IsAddressSplit (Address)) {
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if (((*Pd & IA32_PG_PS) != 0) && IsAddressSplit (Address)) {
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//
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// Based on current page table, create 4KB page table for split area.
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//
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ASSERT (Address == (*Pte & PHYSICAL_ADDRESS_MASK));
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ASSERT (Address == (*Pd & PHYSICAL_ADDRESS_MASK));
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Pt = AllocatePageTableMemory (1);
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ASSERT (Pt != NULL);
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// Split it
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for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++) {
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Pt[Level4] = Address + ((Level4 << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
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for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++) {
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Pt[PtIndex] = Address + ((PtIndex << 12) | mAddressEncMask | PAGE_ATTRIBUTE_BITS);
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} // end for PT
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*Pte = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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*Pd = (UINT64)(UINTN)Pt | mAddressEncMask | PAGE_ATTRIBUTE_BITS;
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} // end if IsAddressSplit
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} // end for PTE
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} // end for PDE
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}
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} // end for PD
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} // end for PDPT
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} // end for PML4
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//
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// Go through page table and set several page table entries to absent or execute-disable.
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//
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DEBUG ((EFI_D_INFO, "Patch page table start ...\n"));
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for (Level1 = 0; Level1 < NumberOfPml4Entries; Level1++) {
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for (Pml4Index = 0; Pml4Index < NumberOfPml4Entries; Pml4Index++) {
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if (sizeof (UINTN) == sizeof (UINT64)) {
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if ((Pml4[Level1] & IA32_PG_P) == 0) {
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if ((Pml4[Pml4Index] & IA32_PG_P) == 0) {
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//
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// If Pml4 entry does not exist, skip it
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// If PML4 entry does not exist, skip it
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//
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continue;
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}
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Pde = (UINT64 *)(UINTN)(Pml4[Level1] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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Pdpt = (UINT64 *)(UINTN)(Pml4[Pml4Index] & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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} else {
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Pde = (UINT64*)(UINTN)mSmmProfileCr3;
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Pdpt = (UINT64*)(UINTN)mSmmProfileCr3;
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}
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for (Level2 = 0; Level2 < NumberOfPdpEntries; Level2++, Pde++) {
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if ((*Pde & IA32_PG_P) == 0) {
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for (PdptIndex = 0; PdptIndex < NumberOfPdptEntries; PdptIndex++, Pdpt++) {
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if ((*Pdpt & IA32_PG_P) == 0) {
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//
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// If PDE entry does not exist, skip it
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// If PDPT entry does not exist, skip it
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//
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continue;
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}
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if ((*Pde & IA32_PG_PS) != 0) {
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if ((*Pdpt & IA32_PG_PS) != 0) {
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//
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// This is 1G entry, set NX bit and skip it
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//
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if (mXdSupported) {
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*Pde = *Pde | IA32_PG_NX;
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*Pdpt = *Pdpt | IA32_PG_NX;
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}
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continue;
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}
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Pte = (UINT64 *)(UINTN)(*Pde & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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if (Pte == 0) {
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Pd = (UINT64 *)(UINTN)(*Pdpt & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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if (Pd == 0) {
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continue;
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}
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for (Level3 = 0; Level3 < SIZE_4KB / sizeof (*Pte); Level3++, Pte++) {
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if ((*Pte & IA32_PG_P) == 0) {
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for (PdIndex = 0; PdIndex < SIZE_4KB / sizeof (*Pd); PdIndex++, Pd++) {
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if ((*Pd & IA32_PG_P) == 0) {
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//
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// If PTE entry does not exist, skip it
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// If PD entry does not exist, skip it
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//
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continue;
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}
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Address = (((Level2 << 9) + Level3) << 21);
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Address = (((PdptIndex << 9) + PdIndex) << 21);
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if ((*Pte & IA32_PG_PS) != 0) {
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if ((*Pd & IA32_PG_PS) != 0) {
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// 2MB page
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if (!IsAddressValid (Address, &Nx)) {
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//
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// Patch to remove Present flag and RW flag
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//
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*Pte = *Pte & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
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*Pd = *Pd & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
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}
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if (Nx && mXdSupported) {
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*Pte = *Pte | IA32_PG_NX;
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*Pd = *Pd | IA32_PG_NX;
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}
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} else {
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// 4KB page
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Pt = (UINT64 *)(UINTN)(*Pte & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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Pt = (UINT64 *)(UINTN)(*Pd & ~mAddressEncMask & PHYSICAL_ADDRESS_MASK);
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if (Pt == 0) {
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continue;
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}
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for (Level4 = 0; Level4 < SIZE_4KB / sizeof(*Pt); Level4++, Pt++) {
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for (PtIndex = 0; PtIndex < SIZE_4KB / sizeof(*Pt); PtIndex++, Pt++) {
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if (!IsAddressValid (Address, &Nx)) {
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*Pt = *Pt & (INTN)(INT32)(~PAGE_ATTRIBUTE_BITS);
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}
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@ -702,9 +702,9 @@ InitPaging (
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Address += SIZE_4KB;
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} // end for PT
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} // end if PS
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} // end for PTE
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} // end for PDE
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}
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} // end for PD
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} // end for PDPT
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} // end for PML4
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//
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// Flush TLB
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