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UefiCpuPkg/PiSmmCpuDxeSmm: Save SMM ranges info into global variables

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v2:
  Add #define SMRR_MAX_ADDRESS to clarify SMRR requirement.

Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Cc: Feng Tian <feng.tian@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
This commit is contained in:
Jeff Fan 2017-03-28 08:48:17 +08:00
parent 4ef6c3850e
commit 7ed6f78145
2 changed files with 29 additions and 21 deletions
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44
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
View File

@ -108,6 +108,12 @@ UINT64 mAddressEncMask = 0;
// //
SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL; SPIN_LOCK *mConfigSmmCodeAccessCheckLock = NULL;
//
// Saved SMM ranges information
//
EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
UINTN mSmmCpuSmramRangeCount;
/** /**
Initialize IDT to setup exception handlers for SMM. Initialize IDT to setup exception handlers for SMM.
@ -971,8 +977,6 @@ FindSmramInfo (
UINTN Size; UINTN Size;
EFI_SMM_ACCESS2_PROTOCOL *SmmAccess; EFI_SMM_ACCESS2_PROTOCOL *SmmAccess;
EFI_SMRAM_DESCRIPTOR *CurrentSmramRange; EFI_SMRAM_DESCRIPTOR *CurrentSmramRange;
EFI_SMRAM_DESCRIPTOR *SmramRanges;
UINTN SmramRangeCount;
UINTN Index; UINTN Index;
UINT64 MaxSize; UINT64 MaxSize;
BOOLEAN Found; BOOLEAN Found;
@ -990,31 +994,31 @@ FindSmramInfo (
Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL); Status = SmmAccess->GetCapabilities (SmmAccess, &Size, NULL);
ASSERT (Status == EFI_BUFFER_TOO_SMALL); ASSERT (Status == EFI_BUFFER_TOO_SMALL);
SmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size); mSmmCpuSmramRanges = (EFI_SMRAM_DESCRIPTOR *)AllocatePool (Size);
ASSERT (SmramRanges != NULL); ASSERT (mSmmCpuSmramRanges != NULL);
Status = SmmAccess->GetCapabilities (SmmAccess, &Size, SmramRanges); Status = SmmAccess->GetCapabilities (SmmAccess, &Size, mSmmCpuSmramRanges);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);
SmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR); mSmmCpuSmramRangeCount = Size / sizeof (EFI_SMRAM_DESCRIPTOR);
// //
// Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size // Find the largest SMRAM range between 1MB and 4GB that is at least 256K - 4K in size
// //
CurrentSmramRange = NULL; CurrentSmramRange = NULL;
for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < SmramRangeCount; Index++) { for (Index = 0, MaxSize = SIZE_256KB - EFI_PAGE_SIZE; Index < mSmmCpuSmramRangeCount; Index++) {
// //
// Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization // Skip any SMRAM region that is already allocated, needs testing, or needs ECC initialization
// //
if ((SmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) { if ((mSmmCpuSmramRanges[Index].RegionState & (EFI_ALLOCATED | EFI_NEEDS_TESTING | EFI_NEEDS_ECC_INITIALIZATION)) != 0) {
continue; continue;
} }
if (SmramRanges[Index].CpuStart >= BASE_1MB) { if (mSmmCpuSmramRanges[Index].CpuStart >= BASE_1MB) {
if ((SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize) <= BASE_4GB) { if ((mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize) <= SMRR_MAX_ADDRESS) {
if (SmramRanges[Index].PhysicalSize >= MaxSize) { if (mSmmCpuSmramRanges[Index].PhysicalSize >= MaxSize) {
MaxSize = SmramRanges[Index].PhysicalSize; MaxSize = mSmmCpuSmramRanges[Index].PhysicalSize;
CurrentSmramRange = &SmramRanges[Index]; CurrentSmramRange = &mSmmCpuSmramRanges[Index];
} }
} }
} }
@ -1027,19 +1031,19 @@ FindSmramInfo (
do { do {
Found = FALSE; Found = FALSE;
for (Index = 0; Index < SmramRangeCount; Index++) { for (Index = 0; Index < mSmmCpuSmramRangeCount; Index++) {
if (SmramRanges[Index].CpuStart < *SmrrBase && *SmrrBase == (SmramRanges[Index].CpuStart + SmramRanges[Index].PhysicalSize)) { if (mSmmCpuSmramRanges[Index].CpuStart < *SmrrBase &&
*SmrrBase = (UINT32)SmramRanges[Index].CpuStart; *SmrrBase == (mSmmCpuSmramRanges[Index].CpuStart + mSmmCpuSmramRanges[Index].PhysicalSize)) {
*SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize); *SmrrBase = (UINT32)mSmmCpuSmramRanges[Index].CpuStart;
*SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE; Found = TRUE;
} else if ((*SmrrBase + *SmrrSize) == SmramRanges[Index].CpuStart && SmramRanges[Index].PhysicalSize > 0) { } else if ((*SmrrBase + *SmrrSize) == mSmmCpuSmramRanges[Index].CpuStart && mSmmCpuSmramRanges[Index].PhysicalSize > 0) {
*SmrrSize = (UINT32)(*SmrrSize + SmramRanges[Index].PhysicalSize); *SmrrSize = (UINT32)(*SmrrSize + mSmmCpuSmramRanges[Index].PhysicalSize);
Found = TRUE; Found = TRUE;
} }
} }
} while (Found); } while (Found);
FreePool (SmramRanges);
DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize)); DEBUG ((EFI_D_INFO, "SMRR Base: 0x%x, SMRR Size: 0x%x\n", *SmrrBase, *SmrrSize));
} }

6
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.h
View File

@ -1,7 +1,7 @@
/** @file /** @file
Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU. Agent Module to load other modules to deploy SMM Entry Vector for X86 CPU.
Copyright (c) 2009 - 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2009 - 2017, Intel Corporation. All rights reserved.<BR>
Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR> Copyright (c) 2017, AMD Incorporated. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
@ -105,6 +105,8 @@ WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull #define PAGING_2M_ADDRESS_MASK_64 0x000FFFFFFFE00000ull
#define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull #define PAGING_1G_ADDRESS_MASK_64 0x000FFFFFC0000000ull
#define SMRR_MAX_ADDRESS BASE_4GB
typedef enum { typedef enum {
PageNone, PageNone,
Page4K, Page4K,
@ -415,6 +417,8 @@ extern UINTN mSemaphoreSize;
extern SPIN_LOCK *mPFLock; extern SPIN_LOCK *mPFLock;
extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock; extern SPIN_LOCK *mConfigSmmCodeAccessCheckLock;
extern SPIN_LOCK *mMemoryMappedLock; extern SPIN_LOCK *mMemoryMappedLock;
extern EFI_SMRAM_DESCRIPTOR *mSmmCpuSmramRanges;
extern UINTN mSmmCpuSmramRangeCount;
// //
// Copy of the PcdPteMemoryEncryptionAddressOrMask // Copy of the PcdPteMemoryEncryptionAddressOrMask