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Add a DMA lib for the OMAP. It is a combination of PCI IO (generic ARM) DMA functions and OMAP specific DMA config routines. Update PCI emulation driver to use the new library. Started converting MMCHS (SD Card) driver over to using DMA, still a work in progress. Need to verify the 22 parameters required to setup a DMA transfer. 

git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10469 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
andrewfish 2010-05-08 19:32:03 +00:00
parent 6191913fb4
commit 7f814ffd44
14 changed files with 840 additions and 178 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

200
Omap35xxPkg/Include/Library/OmapDmaLib.h Executable file
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@ -0,0 +1,200 @@
/** @file
Abstractions for simple OMAP DMA. The DMA functions are modeled on
the PCI IO protocol and follow the same rules as outlined in the UEFI specification.
OMAP_DMA4 structure elements are described in the OMAP35xx TRM. Currently
there is no PCI'less DMA protocol, if one existed it could be used to
replace this library.
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#ifndef __OMAP_DMA_LIB_H__
#define __OMAP_DMA_LIB_H__
typedef enum {
///
/// A read operation from system memory by a bus master.
///
MapOperationBusMasterRead,
///
/// A write operation from system memory by a bus master.
///
MapOperationBusMasterWrite,
///
/// Provides both read and write access to system memory by both the processor and a
/// bus master. The buffer is coherent from both the processor's and the bus master's point of view.
///
MapOperationBusMasterCommonBuffer,
MapOperationMaximum
} DMA_MAP_OPERATION;
// Example from DMA chapter of the OMAP35xx spec
typedef struct {
UINT8 DataType; // DMA4_CSDPi[1:0]
UINT8 ReadPortAccessType; // DMA4_CSDPi[8:7]
UINT8 WritePortAccessType; // DMA4_CSDPi[15:14]
UINT8 SourceEndiansim; // DMA4_CSDPi[21]
UINT8 DestinationEndianism; // DMA4_CSDPi[19]
UINT8 WriteMode; // DMA4_CSDPi[17:16]
UINT8 SourcePacked; // DMA4_CSDPi[6]
UINT8 DestinationPacked; // DMA4_CSDPi[13]
UINT32 NumberOfElementPerFrame; // DMA4_CENi
UINT32 NumberOfFramePerTransferBlock; // DMA4_CFNi
UINT32 SourceStartAddress; // DMA4_CSSAi
UINT32 DestinationStartAddress; // DMA4_CDSAi
UINT32 SourceElementIndex; // DMA4_CSEi
UINT32 SourceFrameIndex; // DMA4_CSFi
UINT32 DestinationElementIndex; // DMA4_CDEi
UINT32 DestinationFrameIndex; // DMA4_CDFi
UINT8 ReadPortAccessMode; // DMA4_CCRi[13:12]
UINT8 WritePortAccessMode; // DMA4_CCRi[15:14]
UINT8 ReadPriority; // DMA4_CCRi[6]
UINT8 WritePriority; // DMA4_CCRi[23]
UINT8 ReadRequestNumber; // DMA4_CCRi[4:0]
UINT8 WriteRequestNumber; // DMA4_CCRi[20:19]
} OMAP_DMA4;
/**
Configure OMAP DMA Channel
@param Channel DMA Channel to configure
@param Dma4 Pointer to structure used to initialize DMA registers for the Channel
@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
@retval EFI_INVALID_PARAMETER Channel is not valid
@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
**/
EFI_STATUS
EFIAPI
EnableDmaChannel (
IN UINTN Channel,
IN OMAP_DMA4 *Dma4
);
/**
Turn of DMA channel configured by EnableDma().
@param Channel DMA Channel to configure
@retval EFI_SUCCESS DMA hardware disabled
@retval EFI_INVALID_PARAMETER Channel is not valid
@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
**/
EFI_STATUS
EFIAPI
DisableDmaChannel (
IN UINTN Channel
);
/**
Provides the DMA controller-specific addresses needed to access system memory.
Operation is relative to the DMA bus master.
@param Operation Indicates if the bus master is going to read or write to system memory.
@param HostAddress The system memory address to map to the DMA controller.
@param NumberOfBytes On input the number of bytes to map. On output the number of bytes
that were mapped.
@param DeviceAddress The resulting map address for the bus master controller to use to
access the hosts HostAddress.
@param Mapping A resulting value to pass to Unmap().
@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
**/
EFI_STATUS
EFIAPI
DmaMap (
IN DMA_MAP_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
);
/**
Completes the DmaMapBusMasterRead(), DmaMapBusMasterWrite(), or DmaMapBusMasterCommonBuffer()
operation and releases any corresponding resources.
@param Mapping The mapping value returned from DmaMap*().
@retval EFI_SUCCESS The range was unmapped.
@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
**/
EFI_STATUS
EFIAPI
DmaUnmap (
IN VOID *Mapping
);
/**
Allocates pages that are suitable for an DmaMap() of type MapOperationBusMasterCommonBuffer.
mapping.
@param MemoryType The type of memory to allocate, EfiBootServicesData or
EfiRuntimeServicesData.
@param Pages The number of pages to allocate.
@param HostAddress A pointer to store the base system memory address of the
allocated range.
@retval EFI_SUCCESS The requested memory pages were allocated.
@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
MEMORY_WRITE_COMBINE and MEMORY_CACHED.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
**/
EFI_STATUS
EFIAPI
DmaAllocateBuffer (
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress
);
/**
Frees memory that was allocated with DmaAllocateBuffer().
@param Pages The number of pages to free.
@param HostAddress The base system memory address of the allocated range.
@retval EFI_SUCCESS The requested memory pages were freed.
@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
was not allocated with DmaAllocateBuffer().
**/
EFI_STATUS
EFIAPI
DmaFreeBuffer (
IN UINTN Pages,
IN VOID *HostAddress
);
#endif

7
Omap35xxPkg/Include/Library/OmapLib.h
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@ -1,6 +1,6 @@
/** @file /** @file
Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -16,24 +16,29 @@
#define __OMAPLIB_H__ #define __OMAPLIB_H__
UINT32 UINT32
EFIAPI
GpioBase ( GpioBase (
IN UINTN Port IN UINTN Port
); );
UINT32 UINT32
EFIAPI
TimerBase ( TimerBase (
IN UINTN Timer IN UINTN Timer
); );
UINTN UINTN
EFIAPI
InterruptVectorForTimer ( InterruptVectorForTimer (
IN UINTN TImer IN UINTN TImer
); );
UINT32 UINT32
EFIAPI
UartBase ( UartBase (
IN UINTN Uart IN UINTN Uart
); );
#endif // __OMAPLIB_H__ #endif // __OMAPLIB_H__

30
Omap35xxPkg/Include/Omap3530/Omap3530Dma.h
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@ -15,18 +15,24 @@
#ifndef __OMAP3530DMA_H__ #ifndef __OMAP3530DMA_H__
#define __OMAP3530DMA_H__ #define __OMAP3530DMA_H__
#define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(i)))
#define DMA4_CCR(_i) (0x48056080 + (0x60*(i))) #define DMA4_MAX_CHANNEL 31
#define DMA4_CICR(_i) (0x48056088 + (0x60*(i)))
#define DMA4_CSDP(_i) (0x48056090 + (0x60*(i))) #define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(_i)))
#define DMA4_CEN(_i) (0x48056094 + (0x60*(i)))
#define DMA4_CFN(_i) (0x48056098 + (0x60*(i))) #define DMA4_CCR(_i) (0x48056080 + (0x60*(_i)))
#define DMA4_CSSA(_i) (0x4805609c + (0x60*(i))) #define DMA4_CICR(_i) (0x48056088 + (0x60*(_i)))
#define DMA4_CDSA(_i) (0x480560a0 + (0x60*(i))) #define DMA4_CSDP(_i) (0x48056090 + (0x60*(_i)))
#define DMA4_CSE(_i) (0x480560a4 + (0x60*(i))) #define DMA4_CEN(_i) (0x48056094 + (0x60*(_i)))
#define DMA4_CSF(_i) (0x480560a8 + (0x60*(i))) #define DMA4_CFN(_i) (0x48056098 + (0x60*(_i)))
#define DMA4_CDE(_i) (0x480560ac + (0x60*(i))) #define DMA4_CSSA(_i) (0x4805609c + (0x60*(_i)))
#define DMA4_CDSA(_i) (0x480560a0 + (0x60*(_i)))
#define DMA4_CSEI(_i) (0x480560a4 + (0x60*(_i)))
#define DMA4_CSFI(_i) (0x480560a8 + (0x60*(_i)))
#define DMA4_CDEI(_i) (0x480560ac + (0x60*(_i)))
#define DMA4_CDFI(_i) (0x480560b0 + (0x60*(_i)))
#define DMA4_GCR (0x48056078)
// Channel Source Destination parameters // Channel Source Destination parameters
#define DMA4_CSDP_DATA_TYPE8 0 #define DMA4_CSDP_DATA_TYPE8 0
@ -98,5 +104,7 @@
#define DMA4_CCR_CONST_FILL_ENABLE BIT16 #define DMA4_CCR_CONST_FILL_ENABLE BIT16
#define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17 #define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17
#define DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE BIT24
#endif #endif

3
Omap35xxPkg/Include/Omap3530/Omap3530MMCHS.h
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@ -199,6 +199,9 @@
#define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE) #define CMD24 (INDX(24) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | DDIR_WRITE)
#define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN) #define CMD24_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BWR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD25 (INDX(25) | DP_ENABLE | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS | MSBS_MULTBLK | DDIR_READ | BCE_ENABLE | DE_ENABLE)
#define CMD25_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | TC_EN | BRR_EN | CTO_EN | DTO_EN | DCRC_EN | DEB_EN | CEB_EN)
#define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS) #define CMD55 (INDX(55) | CICE_ENABLE | CCCE_ENABLE | RSP_TYPE_48BITS)
#define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN) #define CMD55_INT_EN (CERR_EN | CIE_EN | CCRC_EN | CC_EN | CEB_EN | CTO_EN)

348
Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.c Executable file
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@ -0,0 +1,348 @@
/** @file
OMAP35xx DMA abstractions modeled on PCI IO protocol. EnableDma()/DisableDma()
are from OMAP35xx TRM.
Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at
http://opensource.org/licenses/bsd-license.php
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
**/
#include <Base.h>
#include <Library/DebugLib.h>
#include <Library/OmapDmaLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/UncachedMemoryAllocationLib.h>
#include <Library/IoLib.h>
#include <Omap3530/Omap3530.h>
#include <Protocol/Cpu.h>
typedef struct {
EFI_PHYSICAL_ADDRESS HostAddress;
EFI_PHYSICAL_ADDRESS DeviceAddress;
UINTN NumberOfBytes;
DMA_MAP_OPERATION Operation;
} MAP_INFO_INSTANCE;
EFI_CPU_ARCH_PROTOCOL *gCpu;
/**
Configure OMAP DMA Channel
@param Channel DMA Channel to configure
@param Dma4 Pointer to structure used to initialize DMA registers for the Channel
@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
@retval EFI_INVALID_PARAMETER Channel is not valid
@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
**/
EFI_STATUS
EFIAPI
EnableDmaChannel (
IN UINTN Channel,
IN OMAP_DMA4 *DMA4
)
{
UINT32 RegVal;
if (Channel > DMA4_MAX_CHANNEL) {
return EFI_INVALID_PARAMETER;
}
/* 1) Configure the transfer parameters in the logical DMA registers */
/*-------------------------------------------------------------------*/
/* a) Set the data type CSDP[1:0], the Read/Write Port access type
CSDP[8:7]/[15:14], the Source/dest endianism CSDP[21]/CSDP[19],
write mode CSDP[17:16], source/dest packed or nonpacked CSDP[6]/CSDP[13] */
// Read CSDP
RegVal = MmioRead32 (DMA4_CSDP (Channel));
// Build reg
RegVal = ((RegVal & ~ 0x3) | DMA4->DataType );
RegVal = ((RegVal & ~(0x3 << 7)) | (DMA4->ReadPortAccessType << 7));
RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessType << 14));
RegVal = ((RegVal & ~(0x1 << 21)) | (DMA4->SourceEndiansim << 21));
RegVal = ((RegVal & ~(0x1 << 19)) | (DMA4->DestinationEndianism << 19));
RegVal = ((RegVal & ~(0x3 << 16)) | (DMA4->WriteMode << 16));
RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->SourcePacked << 6));
RegVal = ((RegVal & ~(0x1 << 13)) | (DMA4->DestinationPacked << 13));
// Write CSDP
MmioWrite32 (DMA4_CSDP (Channel), RegVal);
/* b) Set the number of element per frame CEN[23:0]*/
MmioWrite32 (DMA4_CEN (Channel), DMA4->NumberOfElementPerFrame);
/* c) Set the number of frame per block CFN[15:0]*/
MmioWrite32 (DMA4_CFN (Channel), DMA4->NumberOfFramePerTransferBlock);
/* d) Set the Source/dest start address index CSSA[31:0]/CDSA[31:0]*/
MmioWrite32 (DMA4_CSSA (Channel), DMA4->SourceStartAddress);
MmioWrite32 (DMA4_CDSA (Channel), DMA4->DestinationStartAddress);
/* e) Set the Read Port addressing mode CCR[13:12], the Write Port addressing mode CCR[15:14],
read/write priority CCR[6]/CCR[26]
I changed LCH CCR[20:19]=00 and CCR[4:0]=00000 to
LCH CCR[20:19]= DMA4->WriteRequestNumber and CCR[4:0]=DMA4->ReadRequestNumber
*/
// Read CCR
RegVal = MmioRead32 (DMA4_CCR (Channel));
// Build reg
RegVal = ((RegVal & ~0x1f) | DMA4->ReadRequestNumber);
RegVal = ((RegVal & ~(BIT20 | BIT19)) | DMA4->WriteRequestNumber << 19);
RegVal = ((RegVal & ~(0x3 << 12)) | (DMA4->ReadPortAccessMode << 12));
RegVal = ((RegVal & ~(0x3 << 14)) | (DMA4->WritePortAccessMode << 14));
RegVal = ((RegVal & ~(0x1 << 6)) | (DMA4->ReadPriority << 6));
RegVal = ((RegVal & ~(0x1 << 26)) | (DMA4->WritePriority << 26));
// Write CCR
MmioWrite32 (DMA4_CCR (Channel), RegVal);
/* f)- Set the source element index CSEI[15:0]*/
MmioWrite32 (DMA4_CSEI (Channel), DMA4->SourceElementIndex);
/* - Set the source frame index CSFI[15:0]*/
MmioWrite32 (DMA4_CSFI (Channel), DMA4->SourceFrameIndex);
/* - Set the destination element index CDEI[15:0]*/
MmioWrite32 (DMA4_CDEI (Channel), DMA4->DestinationElementIndex);
/* - Set the destination frame index CDFI[31:0]*/
MmioWrite32 (DMA4_CDFI (Channel), DMA4->DestinationFrameIndex);
/* 2) Start the DMA transfer by Setting the enable bit CCR[7]=1 */
/*--------------------------------------------------------------*/
//write enable bit
MmioOr32 (DMA4_CCR(0), DMA4_CCR_ENABLE); //Launch transfer
return EFI_SUCCESS;
}
/**
Turn of DMA channel configured by EnableDma().
@param Channel DMA Channel to configure
@retval EFI_SUCCESS DMA hardware disabled
@retval EFI_INVALID_PARAMETER Channel is not valid
@retval EFI_DEVICE_ERROR The system hardware could not map the requested information.
**/
EFI_STATUS
EFIAPI
DisableDmaChannel (
IN UINTN Channel
)
{
if (Channel > DMA4_MAX_CHANNEL) {
return EFI_INVALID_PARAMETER;
}
MmioAnd32 (DMA4_CCR(0), ~(DMA4_CCR_ENABLE | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE));
return EFI_SUCCESS;
}
/**
Provides the DMA controller-specific addresses needed to access system memory.
Operation is relative to the DMA bus master.
@param Operation Indicates if the bus master is going to read or write to system memory.
@param HostAddress The system memory address to map to the DMA controller.
@param NumberOfBytes On input the number of bytes to map. On output the number of bytes
that were mapped.
@param DeviceAddress The resulting map address for the bus master controller to use to
access the hosts HostAddress.
@param Mapping A resulting value to pass to Unmap().
@retval EFI_SUCCESS The range was mapped for the returned NumberOfBytes.
@retval EFI_UNSUPPORTED The HostAddress cannot be mapped as a common buffer.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
@retval EFI_OUT_OF_RESOURCES The request could not be completed due to a lack of resources.
@retval EFI_DEVICE_ERROR The system hardware could not map the requested address.
**/
EFI_STATUS
EFIAPI
DmaMap (
IN DMA_MAP_OPERATION Operation,
IN VOID *HostAddress,
IN OUT UINTN *NumberOfBytes,
OUT PHYSICAL_ADDRESS *DeviceAddress,
OUT VOID **Mapping
)
{
MAP_INFO_INSTANCE *Map;
if ( HostAddress == NULL || NumberOfBytes == NULL ||
DeviceAddress == NULL || Mapping == NULL ) {
return EFI_INVALID_PARAMETER;
}
if (Operation >= MapOperationMaximum) {
return EFI_INVALID_PARAMETER;
}
*DeviceAddress = ConvertToPhysicalAddress (HostAddress);
// Remember range so we can flush on the other side
Map = AllocatePool (sizeof (MAP_INFO_INSTANCE));
if (Map == NULL) {
return EFI_OUT_OF_RESOURCES;
}
*Mapping = Map;
Map->HostAddress = (UINTN)HostAddress;
Map->DeviceAddress = *DeviceAddress;
Map->NumberOfBytes = *NumberOfBytes;
Map->Operation = Operation;
// EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);
return EFI_SUCCESS;
}
/**
Completes the DmaMapBusMasterRead(), DmaMapBusMasterWrite(), or DmaMapBusMasterCommonBuffer()
operation and releases any corresponding resources.
@param Mapping The mapping value returned from DmaMap*().
@retval EFI_SUCCESS The range was unmapped.
@retval EFI_DEVICE_ERROR The data was not committed to the target system memory.
**/
EFI_STATUS
EFIAPI
DmaUnmap (
IN VOID *Mapping
)
{
MAP_INFO_INSTANCE *Map;
if (Mapping == NULL) {
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
}
Map = (MAP_INFO_INSTANCE *)Mapping;
if (Map->Operation == MapOperationBusMasterWrite) {
//
// Make sure we read buffer from uncached memory and not the cache
//
gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
}
FreePool (Map);
return EFI_SUCCESS;
}
/**
Allocates pages that are suitable for an DmaMap() of type MapOperationBusMasterCommonBuffer.
mapping.
@param MemoryType The type of memory to allocate, EfiBootServicesData or
EfiRuntimeServicesData.
@param Pages The number of pages to allocate.
@param HostAddress A pointer to store the base system memory address of the
allocated range.
@retval EFI_SUCCESS The requested memory pages were allocated.
@retval EFI_UNSUPPORTED Attributes is unsupported. The only legal attribute bits are
MEMORY_WRITE_COMBINE and MEMORY_CACHED.
@retval EFI_INVALID_PARAMETER One or more parameters are invalid.
@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.
**/EFI_STATUS
EFIAPI
DmaAllocateBuffer (
IN EFI_MEMORY_TYPE MemoryType,
IN UINTN Pages,
OUT VOID **HostAddress
)
{
if (HostAddress == NULL) {
return EFI_INVALID_PARAMETER;
}
//
// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
//
// We used uncached memory to keep coherency
//
if (MemoryType == EfiBootServicesData) {
*HostAddress = UncachedAllocatePages (Pages);
} else if (MemoryType != EfiRuntimeServicesData) {
*HostAddress = UncachedAllocateRuntimePages (Pages);
} else {
return EFI_INVALID_PARAMETER;
}
return EFI_SUCCESS;
}
/**
Frees memory that was allocated with DmaAllocateBuffer().
@param Pages The number of pages to free.
@param HostAddress The base system memory address of the allocated range.
@retval EFI_SUCCESS The requested memory pages were freed.
@retval EFI_INVALID_PARAMETER The memory range specified by HostAddress and Pages
was not allocated with DmaAllocateBuffer().
**/
EFI_STATUS
EFIAPI
DmaFreeBuffer (
IN UINTN Pages,
IN VOID *HostAddress
)
{
if (HostAddress == NULL) {
return EFI_INVALID_PARAMETER;
}
UncachedFreePages (HostAddress, Pages);
return EFI_SUCCESS;
}
EFI_STATUS
EFIAPI
OmapDmaLibConstructor (
IN EFI_HANDLE ImageHandle,
IN EFI_SYSTEM_TABLE *SystemTable
)
{
EFI_STATUS Status;
// Get the Cpu protocol for later use
Status = gBS->LocateProtocol (&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
ASSERT_EFI_ERROR(Status);
return EFI_SUCCESS;
}

48
Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.inf Executable file
View File

@ -0,0 +1,48 @@
#/** @file
#
# Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
# This program and the accompanying materials
# are licensed and made available under the terms and conditions of the BSD License
# which accompanies this distribution. The full text of the license may be found at
# http://opensource.org/licenses/bsd-license.php
#
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
#
#**/
[Defines]
INF_VERSION = 0x00010005
BASE_NAME = OmapDmaLib
FILE_GUID = 09B17D99-BB07-49a8-B0D2-06D6AFCBE3AB
MODULE_TYPE = UEFI_DRIVER
VERSION_STRING = 1.0
LIBRARY_CLASS = OmapDmaLib
CONSTRUCTOR = OmapDmaLibConstructor
[Sources.common]
OmapDmaLib.c
[Packages]
MdePkg/MdePkg.dec
EmbeddedPkg/EmbeddedPkg.dec
ArmPkg/ArmPkg.dec
Omap35xxPkg/Omap35xxPkg.dec
[LibraryClasses]
DebugLib
UefiBootServicesTableLib
MemoryAllocationLib
UncachedMemoryAllocationLib
IoLib
[Protocols]
gEfiCpuArchProtocolGuid
[Guids]
[Pcd]
[Depex]
gEfiCpuArchProtocolGuid

246
Omap35xxPkg/MMCHSDxe/MMCHS.c
View File

@ -21,8 +21,6 @@
**/ **/
#include <Uefi.h>
#include "MMCHS.h" #include "MMCHS.h"
EFI_BLOCK_IO_MEDIA gMMCHSMedia = { EFI_BLOCK_IO_MEDIA gMMCHSMedia = {
@ -223,6 +221,9 @@ CalculateCardCLKD (
MaxDataTransferRate = gCardInfo.CSDData.TRAN_SPEED; MaxDataTransferRate = gCardInfo.CSDData.TRAN_SPEED;
// For SD Cards we would need to send CMD6 to set
// speeds abouve 25MHz. High Speed mode 50 MHz and up
//Calculate Transfer rate unit (Bits 2:0 of TRAN_SPEED) //Calculate Transfer rate unit (Bits 2:0 of TRAN_SPEED)
switch (MaxDataTransferRate & 0x7) { switch (MaxDataTransferRate & 0x7) {
case 0: case 0:
@ -593,9 +594,6 @@ GetCardSpecificData (
//Calculate total number of blocks and max. data transfer rate supported by the detected card. //Calculate total number of blocks and max. data transfer rate supported by the detected card.
GetCardConfigurationData(); GetCardConfigurationData();
//Change MMCHS clock frequency to what detected card can support.
UpdateMMCHSClkFrequency(gCardInfo.ClockFrequencySelect);
return Status; return Status;
} }
@ -641,6 +639,9 @@ PerformCardConfiguration (
return Status; return Status;
} }
//Change MMCHS clock frequency to what detected card can support.
UpdateMMCHSClkFrequency(gCardInfo.ClockFrequencySelect);
return EFI_SUCCESS; return EFI_SUCCESS;
} }
@ -729,27 +730,158 @@ WriteBlockData (
return EFI_SUCCESS; return EFI_SUCCESS;
} }
EFI_STATUS
DmaBlocks (
IN EFI_BLOCK_IO_PROTOCOL *This,
IN UINTN Lba,
IN OUT VOID *Buffer,
IN UINTN BlockCount,
IN OPERATION_TYPE OperationType
)
{
EFI_STATUS Status;
UINTN RetryCount = 0;
UINTN Cmd = 0;
UINTN CmdInterruptEnable;
UINTN CmdArgument;
VOID *BufferMap;
EFI_PHYSICAL_ADDRESS BufferAddress;
OMAP_DMA4 Dma4;
DMA_MAP_OPERATION DmaOperation;
//Populate the command information based on the operation type.
if (OperationType == READ) {
Cmd = CMD18; //Multiple block read
CmdInterruptEnable = CMD18_INT_EN;
DmaOperation = MapOperationBusMasterCommonBuffer;
} else if (OperationType == WRITE) {
Cmd = CMD25; //Multiple block write
CmdInterruptEnable = CMD25_INT_EN;
DmaOperation = MapOperationBusMasterRead;
} else {
return EFI_INVALID_PARAMETER;
}
// Map passed in buffer for DMA xfer
RetryCount = BlockCount * This->Media->BlockSize;
Status = DmaMap (DmaOperation, Buffer, &RetryCount, &BufferAddress, &BufferMap);
if (EFI_ERROR (Status)) {
return Status;
}
#if 0
MmioWrite32 (DMA4_CSDP(0), DMA4_CSDP_DATA_TYPE32 | DMA4_CSDP_SRC_BURST_EN64 | DMA4_CSDP_WRITE_MODE_POSTED);
MmioWrite32 (DMA4_CEN(0), 0x4096); // Channel Element number
MmioWrite32 (DMA4_CFN(0), 0x1); // Channel Frame number
if () {
MmioWrite32 (DMA4_CCR(0), X | DMA4_CCR_FS_PACKET | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE | DMA4_CCR_DST_AMODE_POST_INC | DMA4_CCR_SEL_SRC_DEST_SYNC_SOURCE);
MmioWrite32 (DMA4_CSSA(0), MMCHS_DATA); // Src is SD Card
MmioWrite32 (DMA4_CDSA(0), (UINT32)BufferAddress); // Dst memory
} else {
MmioWrite32 (DMA4_CCR(0), X | DMA4_CCR_FS_PACKET | DMA4_CCR_RD_ACTIVE | DMA4_CCR_WR_ACTIVE | DMA4_CCR_SRC_AMODE_POST_INC);
MmioWrite32 (DMA4_CSSA(0), (UINT32)BufferAddress); // Src memory
MmioWrite32 (DMA4_CDSA(0), MMCHS_DATA); // Dst SD Card
}
MmioWrite32 (DMA4_CSE(0), 1);
MmioWrite32 (DMA4_CSF(0), This->Media->BlockSize);
MmioWrite32 (DMA4_CDE(0), 1);
#endif
Dma4.DataType = 0; // DMA4_CSDPi[1:0]
Dma4.ReadPortAccessType =0; // DMA4_CSDPi[8:7]
Dma4.WritePortAccessType =0; // DMA4_CSDPi[15:14]
Dma4.SourceEndiansim = 0; // DMA4_CSDPi[21]
Dma4.DestinationEndianism = 0; // DMA4_CSDPi[19]
Dma4.WriteMode = 0; // DMA4_CSDPi[17:16]
Dma4.SourcePacked = 0; // DMA4_CSDPi[6]
Dma4.DestinationPacked = 0; // DMA4_CSDPi[13]
Dma4.NumberOfElementPerFrame = 0; // DMA4_CENi
Dma4.NumberOfFramePerTransferBlock = 0; // DMA4_CFNi
Dma4.SourceStartAddress = 0; // DMA4_CSSAi
Dma4.DestinationStartAddress = 0; // DMA4_CDSAi
Dma4.SourceElementIndex = 0; // DMA4_CSEi
Dma4.SourceFrameIndex = 0; // DMA4_CSFi
Dma4.DestinationElementIndex = 0; // DMA4_CDEi
Dma4.DestinationFrameIndex = 0; // DMA4_CDFi
Dma4.ReadPortAccessMode = 0; // DMA4_CCRi[13:12]
Dma4.WritePortAccessMode = 0; // DMA4_CCRi[15:14]
Dma4.ReadPriority = 0; // DMA4_CCRi[6]
Dma4.WritePriority = 0; // DMA4_CCRi[23]
Dma4.ReadRequestNumber = 0; // DMA4_CCRi[4:0]
Dma4.WriteRequestNumber = 0; // DMA4_CCRi[20:19]
EnableDmaChannel (2, &Dma4);
//Set command argument based on the card access mode (Byte mode or Block mode)
if (gCardInfo.OCRData.AccessMode & BIT1) {
CmdArgument = Lba;
} else {
CmdArgument = Lba * This->Media->BlockSize;
}
//Send Command.
Status = SendCmd (Cmd, CmdInterruptEnable, CmdArgument);
if (EFI_ERROR (Status)) {
DEBUG ((EFI_D_ERROR, "CMD fails. Status: %x\n", Status));
return Status;
}
DisableDmaChannel (2);
Status = DmaUnmap (BufferMap);
return Status;
}
EFI_STATUS EFI_STATUS
TransferBlockData ( TransferBlock (
IN EFI_BLOCK_IO_PROTOCOL *This, IN EFI_BLOCK_IO_PROTOCOL *This,
OUT VOID *Buffer, IN UINTN Lba,
IN OUT VOID *Buffer,
IN OPERATION_TYPE OperationType IN OPERATION_TYPE OperationType
) )
{ {
EFI_STATUS Status; EFI_STATUS Status;
UINTN MmcStatus; UINTN MmcStatus;
UINTN RetryCount = 0; UINTN RetryCount = 0;
UINTN Cmd = 0;
UINTN CmdInterruptEnable = 0;
UINTN CmdArgument = 0;
//Populate the command information based on the operation type.
if (OperationType == READ) {
Cmd = CMD17; //Single block read
CmdInterruptEnable = CMD18_INT_EN;
} else if (OperationType == WRITE) {
Cmd = CMD24; //Single block write
CmdInterruptEnable = CMD24_INT_EN;
}
//Set command argument based on the card access mode (Byte mode or Block mode)
if (gCardInfo.OCRData.AccessMode & BIT1) {
CmdArgument = Lba;
} else {
CmdArgument = Lba * This->Media->BlockSize;
}
//Send Command.
Status = SendCmd (Cmd, CmdInterruptEnable, CmdArgument);
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "CMD fails. Status: %x\n", Status));
return Status;
}
//Read or Write data. //Read or Write data.
if (OperationType == READ) { if (OperationType == READ) {
Status = ReadBlockData(This, Buffer); Status = ReadBlockData (This, Buffer);
if (EFI_ERROR(Status)) { if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "ReadBlockData fails.\n")); DEBUG((EFI_D_ERROR, "ReadBlockData fails.\n"));
return Status; return Status;
} }
} else if (OperationType == WRITE) { } else if (OperationType == WRITE) {
Status = WriteBlockData(This, Buffer); Status = WriteBlockData (This, Buffer);
if (EFI_ERROR(Status)) { if (EFI_ERROR(Status)) {
DEBUG((EFI_D_ERROR, "WriteBlockData fails.\n")); DEBUG((EFI_D_ERROR, "WriteBlockData fails.\n"));
return Status; return Status;
@ -891,9 +1023,8 @@ DetectCard (
gMMCHSMedia.ReadOnly = (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23; gMMCHSMedia.ReadOnly = (MmioRead32 (GPIO1_BASE + GPIO_DATAIN) & BIT23) == BIT23;
gMMCHSMedia.MediaPresent = TRUE; gMMCHSMedia.MediaPresent = TRUE;
gMMCHSMedia.MediaId++; gMMCHSMedia.MediaId++;
gMediaChange = FALSE;
DEBUG ((EFI_D_INFO, "SD Card Media Change\n")); DEBUG ((EFI_D_INFO, "SD Card Media Change on Handle 0x%08x\n", gImageHandle));
return Status; return Status;
} }
@ -910,26 +1041,17 @@ SdReadWrite (
{ {
EFI_STATUS Status = EFI_SUCCESS; EFI_STATUS Status = EFI_SUCCESS;
UINTN RetryCount = 0; UINTN RetryCount = 0;
UINTN NumBlocks; UINTN BlockCount;
UINTN Cmd = 0; UINTN BytesToBeTranferedThisPass;
UINTN CmdInterruptEnable = 0; UINTN BytesRemainingToBeTransfered;
UINTN CmdArgument = 0;
EFI_TPL OldTpl; EFI_TPL OldTpl;
BOOLEAN MediaPresentLastTime;
BOOLEAN Update; BOOLEAN Update;
OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
if (Buffer == NULL) {
Status = EFI_INVALID_PARAMETER;
goto Done;
}
Update = FALSE; Update = FALSE;
MediaPresentLastTime = gMMCHSMedia.MediaPresent;
if (gMediaChange) { if (gMediaChange) {
Update = TRUE;
Status = DetectCard (); Status = DetectCard ();
if (EFI_ERROR (Status)) { if (EFI_ERROR (Status)) {
// We detected a removal // We detected a removal
@ -937,8 +1059,6 @@ SdReadWrite (
gMMCHSMedia.LastBlock = 0; gMMCHSMedia.LastBlock = 0;
gMMCHSMedia.BlockSize = 512; // Should be zero but there is a bug in DiskIo gMMCHSMedia.BlockSize = 512; // Should be zero but there is a bug in DiskIo
gMMCHSMedia.ReadOnly = FALSE; gMMCHSMedia.ReadOnly = FALSE;
} else {
Update = TRUE;
} }
gMediaChange = FALSE; gMediaChange = FALSE;
} else if (!gMMCHSMedia.MediaPresent) { } else if (!gMMCHSMedia.MediaPresent) {
@ -946,7 +1066,8 @@ SdReadWrite (
goto Done; goto Done;
} }
if ((MediaPresentLastTime != gMMCHSMedia.MediaPresent) || Update) { if (Update) {
DEBUG ((EFI_D_INFO, "SD Card ReinstallProtocolInterface ()\n"));
gBS->ReinstallProtocolInterface ( gBS->ReinstallProtocolInterface (
gImageHandle, gImageHandle,
&gEfiBlockIoProtocolGuid, &gEfiBlockIoProtocolGuid,
@ -959,7 +1080,12 @@ SdReadWrite (
goto Done; goto Done;
} }
if (Lba > This->Media->LastBlock) { if (Buffer == NULL) {
Status = EFI_INVALID_PARAMETER;
goto Done;
}
if (Lba > This->Media->LastBlock) {
Status = EFI_INVALID_PARAMETER; Status = EFI_INVALID_PARAMETER;
goto Done; goto Done;
} }
@ -976,54 +1102,42 @@ SdReadWrite (
goto Done; goto Done;
} }
//Populate the command information based on the operation type. OldTpl = gBS->RaiseTPL (TPL_NOTIFY);
if (OperationType == READ) {
Cmd = CMD17; //Single block read
CmdInterruptEnable = CMD17_INT_EN;
} else if (OperationType == WRITE) {
Cmd = CMD24; //Single block write
CmdInterruptEnable = CMD24_INT_EN;
}
//Calculate total number of blocks its going to read. BytesRemainingToBeTransfered = BufferSize;
NumBlocks = (BufferSize + (This->Media->BlockSize - 1))/This->Media->BlockSize; while (BytesRemainingToBeTransfered > 0) {
//Set command argument based on the card access mode (Byte mode or Block mode) if (gMediaChange) {
if (gCardInfo.OCRData.AccessMode & BIT1) { Status = EFI_NO_MEDIA;
CmdArgument = (UINTN)Lba; DEBUG ((EFI_D_INFO, "SdReadWrite() EFI_NO_MEDIA due to gMediaChange\n"));
} else { goto DoneRestoreTPL;
CmdArgument = (UINTN)Lba * This->Media->BlockSize; }
}
//BytesToBeTranferedThisPass = (BytesToBeTranferedThisPass >= MAX_MMCHS_TRANSFER_SIZE) ? MAX_MMCHS_TRANSFER_SIZE : BytesRemainingToBeTransfered;
while(NumBlocks) { BytesToBeTranferedThisPass = This->Media->BlockSize;
//Send Command.
Status = SendCmd (Cmd, CmdInterruptEnable, CmdArgument); BlockCount = BytesToBeTranferedThisPass/This->Media->BlockSize;
if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "CMD fails. Status: %x\n", Status)); if (BlockCount > 1) {
goto Done; Status = DmaBlocks (This, Lba, Buffer, BlockCount, OperationType);
} else {
//Transfer a block worth of data.
Status = TransferBlock (This, Lba, Buffer, OperationType);
} }
//Transfer a block worth of data.
Status = TransferBlockData(This, Buffer, OperationType);
if (EFI_ERROR(Status)) { if (EFI_ERROR(Status)) {
DEBUG ((EFI_D_ERROR, "TransferBlockData fails. %x\n", Status)); DEBUG ((EFI_D_ERROR, "TransferBlockData fails. %x\n", Status));
goto Done; goto DoneRestoreTPL;
} }
//Adjust command argument. BytesRemainingToBeTransfered -= BytesToBeTranferedThisPass;
if (gCardInfo.OCRData.AccessMode & BIT1) { Lba += BlockCount;
CmdArgument++; //Increase BlockIndex by one.
} else {
CmdArgument += This->Media->BlockSize; //Increase BlockIndex by BlockSize
}
//Adjust Buffer.
Buffer = (UINT8 *)Buffer + This->Media->BlockSize; Buffer = (UINT8 *)Buffer + This->Media->BlockSize;
NumBlocks--;
} }
Done: DoneRestoreTPL:
gBS->RestoreTPL (OldTpl); gBS->RestoreTPL (OldTpl);
Done:
return Status; return Status;
} }
@ -1205,7 +1319,7 @@ MMCHSInitialize (
ASSERT_EFI_ERROR(Status); ASSERT_EFI_ERROR(Status);
ZeroMem (&gCardInfo, sizeof (CARD_INFO)); ZeroMem (&gCardInfo, sizeof (CARD_INFO));
Status = gBS->CreateEvent (EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK, TimerCallback, NULL, &gTimerEvent); Status = gBS->CreateEvent (EVT_TIMER | EVT_NOTIFY_SIGNAL, TPL_CALLBACK, TimerCallback, NULL, &gTimerEvent);
ASSERT_EFI_ERROR (Status); ASSERT_EFI_ERROR (Status);

4
Omap35xxPkg/MMCHSDxe/MMCHS.h
View File

@ -15,6 +15,8 @@
#ifndef _MMCHS_H_ #ifndef _MMCHS_H_
#define _MMCHS_H_ #define _MMCHS_H_
#include <Uefi.h>
#include <Library/BaseLib.h> #include <Library/BaseLib.h>
#include <Library/MemoryAllocationLib.h> #include <Library/MemoryAllocationLib.h>
#include <Library/DebugLib.h> #include <Library/DebugLib.h>
@ -22,6 +24,8 @@
#include <Library/PcdLib.h> #include <Library/PcdLib.h>
#include <Library/UefiBootServicesTableLib.h> #include <Library/UefiBootServicesTableLib.h>
#include <Library/BaseMemoryLib.h> #include <Library/BaseMemoryLib.h>
#include <Library/OmapLib.h>
#include <Library/OmapDmaLib.h>
#include <Protocol/EmbeddedExternalDevice.h> #include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/BlockIo.h> #include <Protocol/BlockIo.h>

1
Omap35xxPkg/MMCHSDxe/MMCHS.inf
View File

@ -35,6 +35,7 @@
UefiDriverEntryPoint UefiDriverEntryPoint
MemoryAllocationLib MemoryAllocationLib
IoLib IoLib
OmapDmaLib
[Guids] [Guids]

10
Omap35xxPkg/Omap35xxPkg.dec
View File

@ -31,6 +31,16 @@
[Includes.common] [Includes.common]
Include # Root include for the package Include # Root include for the package
[LibraryClasses]
## @libraryclass Abstract location of basic OMAP components
##
OmapLib|Include/Library/OmapLib.h
## @libraryclass Abstract OMAP and ARM DMA, modeled after PCI IO protocol
##
OmapDmaLib|Include/Library/OmapDmaLib.h
[Guids.common] [Guids.common]
gOmap35xxTokenSpaceGuid = { 0x24b09abe, 0x4e47, 0x481c, { 0xa9, 0xad, 0xce, 0xf1, 0x2c, 0x39, 0x23, 0x27} } gOmap35xxTokenSpaceGuid = { 0x24b09abe, 0x4e47, 0x481c, { 0xa9, 0xad, 0xce, 0xf1, 0x2c, 0x39, 0x23, 0x27} }

2
Omap35xxPkg/Omap35xxPkg.dsc
View File

@ -49,6 +49,7 @@
IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf IoLib|MdePkg/Library/BaseIoLibIntrinsic/BaseIoLibIntrinsic.inf
OmapLib|Omap35xxPkg/Library/OmapLib/OmapLib.inf OmapLib|Omap35xxPkg/Library/OmapLib/OmapLib.inf
OmapDmaLib|Omap35xxPkg/Library/OmapDmaLib/OmapDmaLib.inf
MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf MemoryAllocationLib|MdePkg/Library/UefiMemoryAllocationLib/UefiMemoryAllocationLib.inf
UefiLib|MdePkg/Library/UefiLib/UefiLib.inf UefiLib|MdePkg/Library/UefiLib/UefiLib.inf
@ -168,6 +169,7 @@
[Components.common] [Components.common]
Omap35xxPkg/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf Omap35xxPkg/Library/Omap35xxTimerLib/Omap35xxTimerLib.inf
Omap35xxPkg/Library/OmapLib/OmapLib.inf Omap35xxPkg/Library/OmapLib/OmapLib.inf
Omap35xxPkg/Library/OmapLib/OmapDmaLib.inf
Omap35xxPkg/Flash/Flash.inf Omap35xxPkg/Flash/Flash.inf
Omap35xxPkg/MMCHSDxe/MMCHS.inf Omap35xxPkg/MMCHSDxe/MMCHS.inf

93
Omap35xxPkg/PciEmulation/PciEmulation.c
View File

@ -13,9 +13,7 @@
**/ **/
#include "PciEmulation.h" #include "PciEmulation.h"
#include <Omap3530/Omap3530.h>
EFI_CPU_ARCH_PROTOCOL *gCpu;
EMBEDDED_EXTERNAL_DEVICE *gTPS65950; EMBEDDED_EXTERNAL_DEVICE *gTPS65950;
#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44 #define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44
@ -263,41 +261,18 @@ PciIoMap (
OUT VOID **Mapping OUT VOID **Mapping
) )
{ {
MAP_INFO_INSTANCE *Map; DMA_MAP_OPERATION DmaOperation;
EFI_STATUS Status;
if ( HostAddress == NULL || NumberOfBytes == NULL || if (Operation == EfiPciIoOperationBusMasterRead) {
DeviceAddress == NULL || Mapping == NULL ) { DmaOperation = MapOperationBusMasterRead;
} else if (Operation == EfiPciIoOperationBusMasterWrite) {
DmaOperation = MapOperationBusMasterWrite;
} else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {
DmaOperation = MapOperationBusMasterCommonBuffer;
} else {
return EFI_INVALID_PARAMETER; return EFI_INVALID_PARAMETER;
} }
return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);
if (Operation >= EfiPciOperationMaximum) {
return EFI_INVALID_PARAMETER;
}
*DeviceAddress = ConvertToPhysicalAddress (HostAddress);
// Data cache flush (HostAddress, NumberOfBytes);
// Remember range so we can flush on the other side
Status = gBS->AllocatePool (EfiBootServicesData, sizeof (PCI_DMA_MAP), (VOID **) &Map);
if (EFI_ERROR(Status)) {
return EFI_OUT_OF_RESOURCES;
}
*Mapping = Map;
Map->HostAddress = (UINTN)HostAddress;
Map->DeviceAddress = *DeviceAddress;
Map->NumberOfBytes = *NumberOfBytes;
Map->Operation = Operation;
// EfiCpuFlushTypeWriteBack, EfiCpuFlushTypeInvalidate
gCpu->FlushDataCache (gCpu, (EFI_PHYSICAL_ADDRESS)(UINTN)HostAddress, *NumberOfBytes, EfiCpuFlushTypeWriteBackInvalidate);
return EFI_SUCCESS;
} }
EFI_STATUS EFI_STATUS
@ -306,24 +281,7 @@ PciIoUnmap (
IN VOID *Mapping IN VOID *Mapping
) )
{ {
PCI_DMA_MAP *Map; return DmaUnmap (Mapping);
if (Mapping == NULL) {
ASSERT (FALSE);
return EFI_INVALID_PARAMETER;
}
Map = (PCI_DMA_MAP *)Mapping;
if (Map->Operation == EfiPciOperationBusMasterWrite) {
//
// Make sure we read buffer from uncached memory and not the cache
//
gCpu->FlushDataCache (gCpu, Map->HostAddress, Map->NumberOfBytes, EfiCpuFlushTypeInvalidate);
}
FreePool (Map);
return EFI_SUCCESS;
} }
EFI_STATUS EFI_STATUS
@ -337,29 +295,14 @@ PciIoAllocateBuffer (
) )
{ {
if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) { if (Attributes & EFI_PCI_ATTRIBUTE_INVALID_FOR_ALLOCATE_BUFFER) {
// Check this
return EFI_UNSUPPORTED; return EFI_UNSUPPORTED;
} }
if (HostAddress == NULL) { return DmaAllocateBuffer (MemoryType, Pages, HostAddress);
return EFI_INVALID_PARAMETER;
}
//
// The only valid memory types are EfiBootServicesData and EfiRuntimeServicesData
//
// We used uncached memory to keep coherency
//
if (MemoryType == EfiBootServicesData) {
*HostAddress = UncachedAllocatePages (Pages);
} else if (MemoryType != EfiRuntimeServicesData) {
*HostAddress = UncachedAllocateRuntimePages (Pages);
} else {
return EFI_INVALID_PARAMETER;
}
return EFI_SUCCESS;
} }
EFI_STATUS EFI_STATUS
PciIoFreeBuffer ( PciIoFreeBuffer (
IN EFI_PCI_IO_PROTOCOL *This, IN EFI_PCI_IO_PROTOCOL *This,
@ -367,12 +310,7 @@ PciIoFreeBuffer (
IN VOID *HostAddress IN VOID *HostAddress
) )
{ {
if (HostAddress == NULL) { return DmaFreeBuffer (Pages, HostAddress);
return EFI_INVALID_PARAMETER;
}
UncachedFreePages (HostAddress, Pages);
return EFI_SUCCESS;
} }
@ -508,9 +446,6 @@ PciEmulationEntryPoint (
UINT8 PhysicalPorts; UINT8 PhysicalPorts;
UINTN Count; UINTN Count;
// Get the Cpu protocol for later use
Status = gBS->LocateProtocol(&gEfiCpuArchProtocolGuid, NULL, (VOID **)&gCpu);
ASSERT_EFI_ERROR(Status);
//Configure USB host for OMAP3530. //Configure USB host for OMAP3530.
ConfigureUSBHost(); ConfigureUSBHost();

22
Omap35xxPkg/PciEmulation/PciEmulation.h
View File

@ -28,10 +28,9 @@
#include <Library/PciLib.h> #include <Library/PciLib.h>
#include <Library/UefiLib.h> #include <Library/UefiLib.h>
#include <Library/UefiBootServicesTableLib.h> #include <Library/UefiBootServicesTableLib.h>
#include <Library/UncachedMemoryAllocationLib.h> #include <Library/OmapDmaLib.h>
#include <Protocol/EmbeddedExternalDevice.h> #include <Protocol/EmbeddedExternalDevice.h>
#include <Protocol/Cpu.h>
#include <Protocol/DevicePath.h> #include <Protocol/DevicePath.h>
#include <Protocol/PciIo.h> #include <Protocol/PciIo.h>
#include <Protocol/PciRootBridgeIo.h> #include <Protocol/PciRootBridgeIo.h>
@ -40,7 +39,9 @@
#include <IndustryStandard/Pci22.h> #include <IndustryStandard/Pci22.h>
#include <IndustryStandard/Acpi.h> #include <IndustryStandard/Acpi.h>
extern EFI_CPU_ARCH_PROTOCOL *gCpu; #include <Omap3530/Omap3530.h>
#define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL #define EFI_RESOURCE_NONEXISTENT 0xFFFFFFFFFFFFFFFFULL
#define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL #define EFI_RESOURCE_LESS 0xFFFFFFFFFFFFFFFEULL
@ -99,21 +100,6 @@ typedef union {
} PTR; } PTR;
typedef struct {
EFI_PHYSICAL_ADDRESS HostAddress;
EFI_PHYSICAL_ADDRESS DeviceAddress;
UINTN NumberOfBytes;
EFI_PCI_IO_PROTOCOL_OPERATION Operation;
} MAP_INFO_INSTANCE;
typedef struct {
EFI_PHYSICAL_ADDRESS HostAddress;
EFI_PHYSICAL_ADDRESS DeviceAddress;
UINTN NumberOfBytes;
EFI_PCI_IO_PROTOCOL_OPERATION Operation;
} PCI_DMA_MAP;
EFI_STATUS EFI_STATUS
EFIAPI EFIAPI

4
Omap35xxPkg/PciEmulation/PciEmulation.inf
View File

@ -40,19 +40,17 @@
UefiBootServicesTableLib UefiBootServicesTableLib
UefiDriverEntryPoint UefiDriverEntryPoint
UefiRuntimeServicesTableLib UefiRuntimeServicesTableLib
UncachedMemoryAllocationLib
IoLib IoLib
OmapDmaLib
[Protocols] [Protocols]
gEfiPciRootBridgeIoProtocolGuid gEfiPciRootBridgeIoProtocolGuid
gEfiDevicePathProtocolGuid gEfiDevicePathProtocolGuid
gEfiPciHostBridgeResourceAllocationProtocolGuid gEfiPciHostBridgeResourceAllocationProtocolGuid
gEfiCpuArchProtocolGuid
gEfiPciIoProtocolGuid gEfiPciIoProtocolGuid
gEmbeddedExternalDeviceProtocolGuid gEmbeddedExternalDeviceProtocolGuid
[Depex] [Depex]
gEfiMetronomeArchProtocolGuid AND gEfiMetronomeArchProtocolGuid AND
gEfiCpuArchProtocolGuid AND
gEmbeddedExternalDeviceProtocolGuid gEmbeddedExternalDeviceProtocolGuid