mirror of https://github.com/acidanthera/audk.git
MdeModulePkg/Usb: Make sure data from HW is no more than expected
Contributed-under: TianoCore Contribution Agreement 1.1 Signed-off-by: Ruiyu Ni <ruiyu.ni@intel.com> Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: Star Zeng <star.zeng@intel.com> Cc: Hao A Wu <hao.a.wu@intel.com> Reviewed-by: Hao Wu <hao.a.wu@intel.com> Reviewed-by: Star Zeng <star.zeng@intel.com>
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@ -1009,9 +1009,12 @@ EhcMonitorAsyncRequests (
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ProcBuf = NULL;
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if (Urb->Result == EFI_USB_NOERROR) {
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ASSERT (Urb->Completed <= Urb->DataLen);
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//
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// Make sure the data received from HW is no more than expected.
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//
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if (Urb->Completed <= Urb->DataLen) {
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ProcBuf = AllocatePool (Urb->Completed);
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}
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if (ProcBuf == NULL) {
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EhcUpdateAsyncRequest (Ehc, Urb);
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@ -2,7 +2,7 @@
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The EHCI register operation routines.
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Copyright (c) 2007 - 2013, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials
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are licensed and made available under the terms and conditions of the BSD License
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which accompanies this distribution. The full text of the license may be found at
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@ -1001,11 +1001,12 @@ UhciMonitorAsyncReqList (
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//
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// Copy the data to temporary buffer if there are some
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// data transferred. We may have zero-length packet
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// data transferred. We may have zero-length packet.
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// Make sure the data received from HW is no more than expected.
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//
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Data = NULL;
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if (QhResult.Complete != 0) {
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if ((QhResult.Complete != 0) && (QhResult.Complete <= AsyncReq->DataLen)) {
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Data = AllocatePool (QhResult.Complete);
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if (Data == NULL) {
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@ -1556,9 +1556,12 @@ XhcMonitorAsyncRequests (
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//
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ProcBuf = NULL;
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if (Urb->Result == EFI_USB_NOERROR) {
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ASSERT (Urb->Completed <= Urb->DataLen);
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//
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// Make sure the data received from HW is no more than expected.
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//
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if (Urb->Completed <= Urb->DataLen) {
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ProcBuf = AllocateZeroPool (Urb->Completed);
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}
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if (ProcBuf == NULL) {
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XhcUpdateAsyncRequest (Xhc, Urb);
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