mirror of https://github.com/acidanthera/audk.git
MdePkg/BaseLib: Added ARM Aarch64 architecture support
Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Harry Liebel <Harry.Liebel@arm.com> Signed-off-by: Olivier Martin <olivier.martin@arm.com> Reviewed-by: Liming Gao <liming.gao@intel.com> git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@14515 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Harry Liebel
oliviermartin
parent
a2cacc9a51
commit
807e2604ab
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@ -146,6 +146,39 @@ typedef struct {
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#endif // defined (MDE_CPU_ARM)
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#endif // defined (MDE_CPU_ARM)
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#if defined (MDE_CPU_AARCH64)
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typedef struct {
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// GP regs
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UINT64 X19;
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UINT64 X20;
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UINT64 X21;
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UINT64 X22;
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UINT64 X23;
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UINT64 X24;
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UINT64 X25;
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UINT64 X26;
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UINT64 X27;
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UINT64 X28;
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UINT64 FP;
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UINT64 LR;
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UINT64 IP0;
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// FP regs
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UINT64 D8;
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UINT64 D9;
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UINT64 D10;
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UINT64 D11;
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UINT64 D12;
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UINT64 D13;
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UINT64 D14;
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UINT64 D15;
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} BASE_LIBRARY_JUMP_BUFFER;
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#define BASE_LIBRARY_JUMP_BUFFER_ALIGNMENT 8
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#endif // defined (MDE_CPU_AARCH64)
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//
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//
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// String Services
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// String Services
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//
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//
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@ -0,0 +1,37 @@
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#------------------------------------------------------------------------------
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#
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# CpuBreakpoint() for AArch64
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#
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# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.p2align 2
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ASM_GLOBAL ASM_PFX(CpuBreakpoint)
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#/**
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# Generates a breakpoint on the CPU.
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#
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# Generates a breakpoint on the CPU. The breakpoint must be implemented such
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# that code can resume normal execution after the breakpoint.
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#
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#**/
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#VOID
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#EFIAPI
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#CpuBreakpoint (
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# VOID
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# );
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#
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ASM_PFX(CpuBreakpoint):
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svc 0xdbdb // Superviser exception. Takes 16bit arg -> Armv7 had 'swi' here.
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ret
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@ -0,0 +1,34 @@
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#------------------------------------------------------------------------------
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#
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# DisableInterrupts() for AArch64
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#
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# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.p2align 2
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ASM_GLOBAL ASM_PFX(DisableInterrupts)
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#/**
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# Disables CPU interrupts.
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#
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#**/
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#VOID
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#EFIAPI
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#DisableInterrupts (
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# VOID
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# );
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#
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ASM_PFX(DisableInterrupts):
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msr daifset, #2
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ret
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@ -0,0 +1,35 @@
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#------------------------------------------------------------------------------
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#
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# EnableInterrupts() for AArch64
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#
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# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.p2align 2
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ASM_GLOBAL ASM_PFX(EnableInterrupts)
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#/**
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# Enables CPU interrupts.
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#
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#**/
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#VOID
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#EFIAPI
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#EnableInterrupts (
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# VOID
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# );
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#
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ASM_PFX(EnableInterrupts):
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msr daifclr, #2
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ret
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@ -0,0 +1,45 @@
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#------------------------------------------------------------------------------
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#
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# GetInterruptState() function for AArch64
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#
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# Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.p2align 2
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ASM_GLOBAL ASM_PFX(GetInterruptState)
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#/**
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# Retrieves the current CPU interrupt state.
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#
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# Returns TRUE is interrupts are currently enabled. Otherwise
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# returns FALSE.
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#
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# @retval TRUE CPU interrupts are enabled.
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# @retval FALSE CPU interrupts are disabled.
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#
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#**/
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#
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#BOOLEAN
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#EFIAPI
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#GetInterruptState (
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# VOID
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# );
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#
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ASM_PFX(GetInterruptState):
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mrs x0, daif
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tst x0, #2 // Check if IRQ is enabled. Enabled if 0.
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mov w0, #0
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mov w1, #1
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csel w0, w1, w0, ne
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ret
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@ -0,0 +1,97 @@
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#------------------------------------------------------------------------------
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#
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# Copyright (c) 2009-2013, ARM Ltd. All rights reserved.
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# This program and the accompanying materials
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# are licensed and made available under the terms and conditions of the BSD License
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# which accompanies this distribution. The full text of the license may be found at
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# http://opensource.org/licenses/bsd-license.php.
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#
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# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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#
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#------------------------------------------------------------------------------
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.text
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.p2align 3
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ASM_GLOBAL ASM_PFX(SetJump)
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ASM_GLOBAL ASM_PFX(InternalLongJump)
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#define GPR_LAYOUT \
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REG_PAIR (x19, x20, 0); \
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REG_PAIR (x21, x22, 16); \
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REG_PAIR (x23, x24, 32); \
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REG_PAIR (x25, x26, 48); \
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REG_PAIR (x27, x28, 64); \
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REG_PAIR (x29, x30, 80);/*FP, LR*/ \
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REG_ONE (x16, 96) /*IP0*/
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#define FPR_LAYOUT \
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REG_PAIR ( d8, d9, 112); \
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REG_PAIR (d10, d11, 128); \
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REG_PAIR (d12, d13, 144); \
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REG_PAIR (d14, d15, 160);
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#/**
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# Saves the current CPU context that can be restored with a call to LongJump() and returns 0.#
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#
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# Saves the current CPU context in the buffer specified by JumpBuffer and returns 0. The initial
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# call to SetJump() must always return 0. Subsequent calls to LongJump() cause a non-zero
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# value to be returned by SetJump().
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#
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# If JumpBuffer is NULL, then ASSERT().
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# For IPF CPUs, if JumpBuffer is not aligned on a 16-byte boundary, then ASSERT().
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#
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# @param JumpBuffer A pointer to CPU context buffer.
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#
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#**/
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#
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#UINTN
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#EFIAPI
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#SetJump (
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# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer // X0
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# );
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#
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ASM_PFX(SetJump):
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mov x16, sp // use IP0 so save SP
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#define REG_PAIR(REG1, REG2, OFFS) stp REG1, REG2, [x0, OFFS]
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#define REG_ONE(REG1, OFFS) str REG1, [x0, OFFS]
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GPR_LAYOUT
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FPR_LAYOUT
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#undef REG_PAIR
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#undef REG_ONE
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mov w0, #0
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ret
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#/**
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# Restores the CPU context that was saved with SetJump().#
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#
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# Restores the CPU context from the buffer specified by JumpBuffer.
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# This function never returns to the caller.
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# Instead is resumes execution based on the state of JumpBuffer.
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#
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# @param JumpBuffer A pointer to CPU context buffer.
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# @param Value The value to return when the SetJump() context is restored.
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#
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#**/
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#VOID
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#EFIAPI
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#InternalLongJump (
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# IN BASE_LIBRARY_JUMP_BUFFER *JumpBuffer, // X0
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# IN UINTN Value // X1
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# );
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#
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ASM_PFX(InternalLongJump):
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#define REG_PAIR(REG1, REG2, OFFS) ldp REG1, REG2, [x0, OFFS]
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#define REG_ONE(REG1, OFFS) ldr REG1, [x0, OFFS]
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GPR_LAYOUT
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FPR_LAYOUT
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#undef REG_PAIR
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#undef REG_ONE
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mov sp, x16
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cmp w1, #0
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mov w0, #1
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csel w0, w1, w0, ne
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// use br not ret, as ret is guaranteed to mispredict
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br x30
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ASM_FUNCTION_REMOVE_IF_UNREFERENCED
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@ -0,0 +1,68 @@
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//------------------------------------------------------------------------------
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//
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// Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>
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// Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
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// Portions copyright (c) 2011 - 2013, ARM Limited. All rights reserved.<BR>
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// This program and the accompanying materials
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// are licensed and made available under the terms and conditions of the BSD License
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// which accompanies this distribution. The full text of the license may be found at
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// http://opensource.org/licenses/bsd-license.php.
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//
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// THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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// WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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//
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//------------------------------------------------------------------------------
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.text
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.align 5
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ASM_GLOBAL ASM_PFX(InternalSwitchStackAsm)
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ASM_GLOBAL ASM_PFX(CpuPause)
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/**
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//
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// This allows the caller to switch the stack and goes to the new entry point
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//
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// @param EntryPoint The pointer to the location to enter
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// @param Context Parameter to pass in
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// @param Context2 Parameter2 to pass in
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// @param NewStack New Location of the stack
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//
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// @return Nothing. Goes to the Entry Point passing in the new parameters
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//
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VOID
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EFIAPI
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InternalSwitchStackAsm (
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SWITCH_STACK_ENTRY_POINT EntryPoint,
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VOID *Context,
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VOID *Context2,
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VOID *NewStack
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);
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**/
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ASM_PFX(InternalSwitchStackAsm):
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mov x30, x0
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mov sp, x3
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mov x0, x1
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mov x1, x2
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ret
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/**
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//
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// Requests CPU to pause for a short period of time.
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//
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// Requests CPU to pause for a short period of time. Typically used in MP
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// systems to prevent memory starvation while waiting for a spin lock.
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//
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VOID
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EFIAPI
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CpuPause (
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VOID
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)
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**/
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ASM_PFX(CpuPause):
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nop
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nop
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nop
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nop
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nop
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ret
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@ -3,6 +3,7 @@
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#
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#
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# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
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# Copyright (c) 2007 - 2010, Intel Corporation. All rights reserved.<BR>
|
||||||
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
|
||||||
|
# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>
|
||||||
#
|
#
|
||||||
# This program and the accompanying materials
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# This program and the accompanying materials
|
||||||
# are licensed and made available under the terms and conditions of the BSD License
|
# are licensed and made available under the terms and conditions of the BSD License
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@ -23,7 +24,7 @@
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LIBRARY_CLASS = BaseLib
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LIBRARY_CLASS = BaseLib
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#
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#
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# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM
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# VALID_ARCHITECTURES = IA32 X64 IPF EBC ARM AARCH64
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#
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#
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[Sources]
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[Sources]
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@ -476,6 +477,18 @@
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Arm/SetJumpLongJump.S | GCC
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Arm/SetJumpLongJump.S | GCC
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Arm/CpuBreakpoint.S | GCC
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Arm/CpuBreakpoint.S | GCC
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|
|
||||||
|
[Sources.AARCH64]
|
||||||
|
Arm/InternalSwitchStack.c
|
||||||
|
Arm/Unaligned.c
|
||||||
|
Math64.c
|
||||||
|
|
||||||
|
AArch64/SwitchStack.S | GCC
|
||||||
|
AArch64/EnableInterrupts.S | GCC
|
||||||
|
AArch64/DisableInterrupts.S | GCC
|
||||||
|
AArch64/GetInterruptsState.S | GCC
|
||||||
|
AArch64/SetJumpLongJump.S | GCC
|
||||||
|
AArch64/CpuBreakpoint.S | GCC
|
||||||
|
|
||||||
[Packages]
|
[Packages]
|
||||||
MdePkg/MdePkg.dec
|
MdePkg/MdePkg.dec
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue