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DynamicTablesPkg: Move Pci Address Map Info to Arch Common
Move Pci Address Map Info object from Arm Namespace to the Arch Common namespace. Correspondingly also update the following modules to reflect the changes introduced by the move: - SSDT PCIe generator - ConfigurationManagerObjectParser - Dynamic Plat Repo TokenFixer map - FdtHwInfoParserLib/Pci/ArmPciConfigSpaceParser. Cc: Pierre Gondois <Pierre.Gondois@arm.com> Cc: Yeo Reum Yun <YeoReum.Yun@arm.com> Cc: AbdulLateef Attar <AbdulLateef.Attar@amd.com> Cc: Jeshua Smith <jeshuas@nvidia.com> Cc: Jeff Brasen <jbrasen@nvidia.com> Cc: Girish Mahadevan <gmahadevan@nvidia.com> Cc: Leif Lindholm <quic_llindhol@quicinc.com> Cc: Meenakshi Aggarwal <meenakshi.aggarwal@nxp.com> Signed-off-by: Sami Mujawar <sami.mujawar@arm.com> Signed-off-by: Pierre Gondois <pierre.gondois@arm.com> Reviewed-by: Sunil V L <sunilvl@ventanamicro.com>
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@ -29,6 +29,7 @@ typedef enum ArchCommonObjectID {
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EArchCommonObjFixedFeatureFlags, ///< 6 - Fixed feature flags for FADT
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EArchCommonObjCmRef, ///< 7 - CM Object Reference
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EArchCommonObjPciConfigSpaceInfo, ///< 8 - PCI Configuration Space Info
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EArchCommonObjPciAddressMapInfo, ///< 9 - Pci Address Map Info
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EArchCommonObjMax
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} EARCH_COMMON_OBJECT_ID;
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@ -142,6 +143,33 @@ typedef struct CmArchCommonPciConfigSpaceInfo {
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CM_OBJECT_TOKEN InterruptMapToken;
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} CM_ARCH_COMMON_PCI_CONFIG_SPACE_INFO;
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/** A structure that describes a PCI Address Map.
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The memory-ranges used by the PCI bus are described by this object.
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ID: EArchCommonObjPciAddressMapInfo
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*/
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typedef struct CmArchCommonPciAddressMapInfo {
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/** Pci address space code
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Available values are:
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- 0: Configuration Space
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- 1: I/O Space
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- 2: 32-bit-address Memory Space
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- 3: 64-bit-address Memory Space
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*/
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UINT8 SpaceCode;
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/// PCI address
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UINT64 PciAddress;
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/// Cpu address
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UINT64 CpuAddress;
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/// Address size
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UINT64 AddressSize;
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} CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO;
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#pragma pack()
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#endif // ARCH_COMMON_NAMESPACE_OBJECTS_H_
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@ -56,19 +56,18 @@ typedef enum ArmObjectID {
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EArmObjGenericInitiatorAffinityInfo, ///< 25 - Generic Initiator Affinity
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EArmObjCmn600Info, ///< 26 - CMN-600 Info
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EArmObjLpiInfo, ///< 27 - Lpi Info
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EArmObjPciAddressMapInfo, ///< 28 - Pci Address Map Info
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EArmObjPciInterruptMapInfo, ///< 29 - Pci Interrupt Map Info
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EArmObjRmr, ///< 30 - Reserved Memory Range Node
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EArmObjMemoryRangeDescriptor, ///< 31 - Memory Range Descriptor
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EArmObjCpcInfo, ///< 32 - Continuous Performance Control Info
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EArmObjPccSubspaceType0Info, ///< 33 - Pcc Subspace Type 0 Info
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EArmObjPccSubspaceType1Info, ///< 34 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType2Info, ///< 35 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType3Info, ///< 36 - Pcc Subspace Type 3 Info
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EArmObjPccSubspaceType4Info, ///< 37 - Pcc Subspace Type 4 Info
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EArmObjPccSubspaceType5Info, ///< 38 - Pcc Subspace Type 5 Info
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EArmObjEtInfo, ///< 39 - Embedded Trace Extension/Module Info
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EArmObjPsdInfo, ///< 40 - P-State Dependency (PSD) Info
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EArmObjPciInterruptMapInfo, ///< 28 - Pci Interrupt Map Info
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EArmObjRmr, ///< 29 - Reserved Memory Range Node
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EArmObjMemoryRangeDescriptor, ///< 30 - Memory Range Descriptor
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EArmObjCpcInfo, ///< 31 - Continuous Performance Control Info
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EArmObjPccSubspaceType0Info, ///< 32 - Pcc Subspace Type 0 Info
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EArmObjPccSubspaceType1Info, ///< 33 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType2Info, ///< 34 - Pcc Subspace Type 2 Info
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EArmObjPccSubspaceType3Info, ///< 35 - Pcc Subspace Type 3 Info
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EArmObjPccSubspaceType4Info, ///< 36 - Pcc Subspace Type 4 Info
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EArmObjPccSubspaceType5Info, ///< 37 - Pcc Subspace Type 5 Info
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EArmObjEtInfo, ///< 38 - Embedded Trace Extension/Module Info
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EArmObjPsdInfo, ///< 39 - P-State Dependency (PSD) Info
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EArmObjMax
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} EARM_OBJECT_ID;
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@ -901,33 +900,6 @@ typedef struct CmArmLpiInfo {
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CHAR8 StateName[16];
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} CM_ARM_LPI_INFO;
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/** A structure that describes a PCI Address Map.
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The memory-ranges used by the PCI bus are described by this object.
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ID: EArmObjPciAddressMapInfo
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*/
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typedef struct CmArmPciAddressMapInfo {
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/** Pci address space code
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Available values are:
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- 0: Configuration Space
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- 1: I/O Space
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- 2: 32-bit-address Memory Space
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- 3: 64-bit-address Memory Space
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*/
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UINT8 SpaceCode;
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/// PCI address
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UINT64 PciAddress;
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/// Cpu address
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UINT64 CpuAddress;
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/// Address size
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UINT64 AddressSize;
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} CM_ARM_PCI_ADDRESS_MAP_INFO;
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/** A structure that describes a PCI Interrupt Map.
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The legacy PCI interrupts used by PCI devices are described by this object.
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@ -44,7 +44,7 @@ Requirements:
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this Generator:
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- EArchCommonObjCmRef
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- EArchCommonObjPciConfigSpaceInfo
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- EArmObjPciAddressMapInfo
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- EArchCommonObjPciAddressMapInfo
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- EArmObjPciInterruptMapInfo
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*/
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@ -70,9 +70,9 @@ GET_OBJECT_LIST (
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Address Mapping Information from the Configuration Manager.
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*/
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GET_OBJECT_LIST (
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EObjNameSpaceArm,
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EArmObjPciAddressMapInfo,
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CM_ARM_PCI_ADDRESS_MAP_INFO
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EObjNameSpaceArchCommon,
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EArchCommonObjPciAddressMapInfo,
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CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO
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);
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/** This macro expands to a function that retrieves the Pci
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@ -455,14 +455,14 @@ GeneratePciCrs (
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IN OUT AML_OBJECT_NODE_HANDLE PciNode
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)
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{
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EFI_STATUS Status;
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BOOLEAN Translation;
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UINT32 Index;
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CM_ARCH_COMMON_OBJ_REF *RefInfo;
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UINT32 RefCount;
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CM_ARM_PCI_ADDRESS_MAP_INFO *AddrMapInfo;
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AML_OBJECT_NODE_HANDLE CrsNode;
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BOOLEAN IsPosDecode;
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EFI_STATUS Status;
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BOOLEAN Translation;
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UINT32 Index;
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CM_ARCH_COMMON_OBJ_REF *RefInfo;
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UINT32 RefCount;
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CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO *AddrMapInfo;
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AML_OBJECT_NODE_HANDLE CrsNode;
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BOOLEAN IsPosDecode;
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ASSERT (Generator != NULL);
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ASSERT (CfgMgrProtocol != NULL);
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@ -506,7 +506,7 @@ GeneratePciCrs (
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}
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// Get the array of CM_ARCH_COMMON_OBJ_REF referencing the
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// CM_ARM_PCI_ADDRESS_MAP_INFO objects.
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// CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO objects.
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Status = GetEArchCommonObjCmRef (
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CfgMgrProtocol,
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PciInfo->AddressMapToken,
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@ -519,8 +519,8 @@ GeneratePciCrs (
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}
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for (Index = 0; Index < RefCount; Index++) {
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// Get CM_ARM_PCI_ADDRESS_MAP_INFO structures one by one.
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Status = GetEArmObjPciAddressMapInfo (
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// Get CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO structures one by one.
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Status = GetEArchCommonObjPciAddressMapInfo (
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CfgMgrProtocol,
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RefInfo[Index].ReferenceToken,
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&AddrMapInfo,
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@ -171,19 +171,18 @@ CM_OBJECT_TOKEN_FIXER TokenFixer[EArmObjMax] = {
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NULL, ///< 25 - Generic Initiator Affinity
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NULL, ///< 26 - CMN-600 Info
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NULL, ///< 27 - Lpi Info
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NULL, ///< 28 - Pci Address Map Info
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NULL, ///< 29 - Pci Interrupt Map Info
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NULL, ///< 30 - Reserved Memory Range Node
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NULL, ///< 31 - Memory Range Descriptor
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NULL, ///< 32 - Continuous Performance Control Info
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NULL, ///< 33 - Pcc Subspace Type 0 Info
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NULL, ///< 28 - Pci Interrupt Map Info
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NULL, ///< 29 - Reserved Memory Range Node
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NULL, ///< 30 - Memory Range Descriptor
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NULL, ///< 31 - Continuous Performance Control Info
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NULL, ///< 32 - Pcc Subspace Type 0 Info
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NULL, ///< 33 - Pcc Subspace Type 2 Info
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NULL, ///< 34 - Pcc Subspace Type 2 Info
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NULL, ///< 35 - Pcc Subspace Type 2 Info
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NULL, ///< 36 - Pcc Subspace Type 3 Info
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NULL, ///< 37 - Pcc Subspace Type 4 Info
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NULL, ///< 38 - Pcc Subspace Type 5 Info
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NULL, ///< 39 - Embedded Trace Extension/Module Info
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NULL ///< 40 - P-State Dependency (PSD) Info
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NULL, ///< 35 - Pcc Subspace Type 3 Info
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NULL, ///< 36 - Pcc Subspace Type 4 Info
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NULL, ///< 37 - Pcc Subspace Type 5 Info
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NULL, ///< 38 - Embedded Trace Extension/Module Info
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NULL ///< 39 - P-State Dependency (PSD) Info
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};
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/** CmObj token fixer.
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@ -440,9 +440,9 @@ STATIC CONST CM_OBJ_PARSER CmArmLpiInfoParser[] = {
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{ "StateName", 16, NULL, PrintString },
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};
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/** A parser for EArmObjPciAddressMapInfo.
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/** A parser for EArchCommonObjPciAddressMapInfo.
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*/
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STATIC CONST CM_OBJ_PARSER CmArmPciAddressMapInfoParser[] = {
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STATIC CONST CM_OBJ_PARSER CmArchCommonPciAddressMapInfoParser[] = {
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{ "SpaceCode", 1, "%d", NULL },
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{ "PciAddress", 8, "0x%llx", NULL },
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{ "CpuAddress", 8, "0x%llx", NULL },
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@ -679,6 +679,7 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArchCommonNamespaceObjectParser[] = {
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CM_PARSER_ADD_OBJECT (EArchCommonObjFixedFeatureFlags, CmArchCommonFixedFeatureFlagsParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjCmRef, CmArchCommonObjRefParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjPciConfigSpaceInfo, CmArchCommonPciConfigSpaceInfoParser),
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CM_PARSER_ADD_OBJECT (EArchCommonObjPciAddressMapInfo, CmArchCommonPciAddressMapInfoParser),
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CM_PARSER_ADD_OBJECT_RESERVED (EArchCommonObjMax)
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};
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@ -713,7 +714,6 @@ STATIC CONST CM_OBJ_PARSER_ARRAY ArmNamespaceObjectParser[] = {
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CM_PARSER_ADD_OBJECT (EArmObjGenericInitiatorAffinityInfo,CmArmGenericInitiatorAffinityInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjCmn600Info, CmArmCmn600InfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjLpiInfo, CmArmLpiInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjPciAddressMapInfo, CmArmPciAddressMapInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjPciInterruptMapInfo, CmPciInterruptMapInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjRmr, CmArmRmrInfoParser),
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CM_PARSER_ADD_OBJECT (EArmObjMemoryRangeDescriptor, CmArmMemoryRangeDescriptorInfoParser),
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@ -188,8 +188,8 @@ ParseAddressMap (
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UINT32 Count;
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UINT32 PciAddressAttr;
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CM_ARM_PCI_ADDRESS_MAP_INFO *PciAddressMapInfo;
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UINT32 BufferSize;
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CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO *PciAddressMapInfo;
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UINT32 BufferSize;
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// The mapping is done on AddressMapSize bytes.
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AddressMapSize = (PCI_ADDRESS_CELLS + AddressCells + PCI_SIZE_CELLS) *
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@ -208,7 +208,7 @@ ParseAddressMap (
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Count = DataSize / AddressMapSize;
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// Allocate a buffer to store each address mapping.
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BufferSize = Count * sizeof (CM_ARM_PCI_ADDRESS_MAP_INFO);
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BufferSize = Count * sizeof (CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO);
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PciAddressMapInfo = AllocateZeroPool (BufferSize);
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if (PciAddressMapInfo == NULL) {
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ASSERT (0);
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@ -246,9 +246,9 @@ ParseAddressMap (
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} // for
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PciInfo->Mapping[PciMappingTableAddress].ObjectId =
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CREATE_CM_ARM_OBJECT_ID (EArmObjPciAddressMapInfo);
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CREATE_CM_ARCH_COMMON_OBJECT_ID (EArchCommonObjPciAddressMapInfo);
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PciInfo->Mapping[PciMappingTableAddress].Size =
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sizeof (CM_ARM_PCI_ADDRESS_MAP_INFO) * Count;
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sizeof (CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO) * Count;
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PciInfo->Mapping[PciMappingTableAddress].Data = PciAddressMapInfo;
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PciInfo->Mapping[PciMappingTableAddress].Count = Count;
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@ -413,7 +413,7 @@ ParseIrqMap (
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// Allocate a buffer to store each interrupt mapping.
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IrqMapCount = DataSize / IrqMapSize;
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BufferSize = IrqMapCount * sizeof (CM_ARM_PCI_ADDRESS_MAP_INFO);
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BufferSize = IrqMapCount * sizeof (CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO);
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PciInterruptMapInfo = AllocateZeroPool (BufferSize);
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if (PciInterruptMapInfo == NULL) {
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ASSERT (0);
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@ -580,7 +580,7 @@ PciNodeParser (
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CmObj of the following types are concerned:
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- EArchCommonObjPciConfigSpaceInfo
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- EArmObjPciAddressMapInfo
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- EArchCommonObjPciAddressMapInfo
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- EArmObjPciInterruptMapInfo
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@param [in] FdtParserHandle A handle to the parser instance.
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@ -694,12 +694,12 @@ FreeParserTable (
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UINT8 EndBusNumber; // {Populated}
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} CM_ARCH_COMMON_PCI_CONFIG_SPACE_INFO;
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typedef struct CmArmPciAddressMapInfo {
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typedef struct CmArchCommonPciAddressMapInfo {
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UINT8 SpaceCode; // {Populated}
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UINT64 PciAddress; // {Populated}
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UINT64 CpuAddress; // {Populated}
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UINT64 AddressSize; // {Populated}
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} CM_ARM_PCI_ADDRESS_MAP_INFO;
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} CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO;
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typedef struct CmArmPciInterruptMapInfo {
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UINT8 PciBus; // {Populated}
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@ -102,12 +102,12 @@ typedef struct PciParserTable {
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UINT8 EndBusNumber; // {Populated}
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} CM_ARCH_COMMON_PCI_CONFIG_SPACE_INFO;
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typedef struct CmArmPciAddressMapInfo {
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typedef struct CmArchCommonPciAddressMapInfo {
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UINT8 SpaceCode; // {Populated}
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UINT64 PciAddress; // {Populated}
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UINT64 CpuAddress; // {Populated}
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UINT64 AddressSize; // {Populated}
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} CM_ARM_PCI_ADDRESS_MAP_INFO;
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} CM_ARCH_COMMON_PCI_ADDRESS_MAP_INFO;
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typedef struct CmArmPciInterruptMapInfo {
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UINT8 PciBus; // {Populated}
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@ -468,19 +468,18 @@ The CM_OBJECT_ID type is used to identify the Configuration Manager
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| 25 | Generic Initiator Affinity Info | Move to Arch Common NS |
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| 26 | CMN 600 Info | |
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| 27 | Low Power Idle State Info | Move to Arch Common NS |
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| 28 | PCI Address Map Info | Move to Arch Common NS |
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| 29 | PCI Interrupt Map Info | Move to Arch Common NS |
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| 30 | Reserved Memory Range Node | |
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| 31 | Memory Range Descriptor | |
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| 32 | Continuous Performance Control Info | Move to Arch Common NS |
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| 33 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
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| 34 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
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| 35 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
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| 36 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
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| 37 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
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| 38 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
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| 39 | Embedded Trace Extension/Module Info | |
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| 40 | P-State Dependency (PSD) Info | Move to Arch Common NS |
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| 28 | PCI Interrupt Map Info | Move to Arch Common NS |
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| 29 | Reserved Memory Range Node | |
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| 30 | Memory Range Descriptor | |
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| 31 | Continuous Performance Control Info | Move to Arch Common NS |
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| 32 | Pcc Subspace Type 0 Info | Move to Arch Common NS |
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| 33 | Pcc Subspace Type 1 Info | Move to Arch Common NS |
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| 34 | Pcc Subspace Type 2 Info | Move to Arch Common NS |
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| 35 | Pcc Subspace Type 3 Info | Move to Arch Common NS |
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| 36 | Pcc Subspace Type 4 Info | Move to Arch Common NS |
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| 37 | Pcc Subspace Type 5 Info | Move to Arch Common NS |
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| 38 | Embedded Trace Extension/Module Info | |
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| 39 | P-State Dependency (PSD) Info | Move to Arch Common NS |
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| `*` | All other values are reserved. | |
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#### Object ID's in the Arch Common Namespace:
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@ -496,4 +495,5 @@ The CM_OBJECT_ID type is used to identify the Configuration Manager
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| 6 | Fixed feature flags for FADT | |
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| 7 | CM Object Reference | |
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| 8 | PCI Configuration Space Info | |
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| 9 | PCI Address Map Info | |
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| `*` | All other values are reserved. | |
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