tyler.durden
/
audk
mirror of https://github.com/acidanthera/audk.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

MdeModulePkg: Replace Opcode with the corresponding instructions. 

REF: https://bugzilla.tianocore.org/show_bug.cgi?id=3790

Replace Opcode with the corresponding instructions.
The code changes have been verified with CompareBuild.py tool, which
can be used to compare the results of two different EDK II builds to
determine if they generate the same binaries.
(tool link: https://github.com/mdkinney/edk2/tree/sandbox/CompareBuild)

Signed-off-by: Jason Lou <yun.lou@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Cc: Dandan Bi <dandan.bi@intel.com>
Reviewed-by: Liming Gao <gaoliming@byosoft.com.cn>
This commit is contained in:
Jason 2022-01-10 21:04:09 +08:00 committed by mergify[bot]
parent b1b89f9009
commit 84338c0d49
2 changed files with 6 additions and 35 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

20
MdeModulePkg/Universal/DebugSupportDxe/Ia32/AsmFuncs.nasm
View File

@ -1,7 +1,7 @@
;/** @file ;/** @file
; Low leve IA32 specific debug support functions. ; Low leve IA32 specific debug support functions.
; ;
; Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2006 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
;**/ ;**/
@ -26,20 +26,6 @@
%define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags %define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags
;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87,
;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver
;; MUST check the CPUID feature flags to see that these instructions are available
;; and fail to init if they are not.
;; fxstor [edi]
%macro FXSTOR_EDI 0
db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [edi]
%endmacro
;; fxrstor [esi]
%macro FXRSTOR_ESI 0
db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [esi]
%endmacro
SECTION .data SECTION .data
global ASM_PFX(OrigVector) global ASM_PFX(OrigVector)
@ -348,7 +334,7 @@ ExtraPushDone:
; IMPORTANT!! The debug stack has been carefully constructed to ; IMPORTANT!! The debug stack has been carefully constructed to
; insure that esp and edi are 16 byte aligned when we get here. ; insure that esp and edi are 16 byte aligned when we get here.
; They MUST be. If they are not, a GP fault will occur. ; They MUST be. If they are not, a GP fault will occur.
FXSTOR_EDI fxsave [edi]
;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear ;; UEFI calling convention for IA32 requires that Direction flag in EFLAGs is clear
cld cld
@ -372,7 +358,7 @@ ExtraPushDone:
;; FX_SAVE_STATE_IA32 FxSaveState; ;; FX_SAVE_STATE_IA32 FxSaveState;
mov esi, esp mov esi, esp
FXRSTOR_ESI fxrstor [esi]
add esp, 512 add esp, 512
;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; ;; UINT32 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;

21
MdeModulePkg/Universal/DebugSupportDxe/X64/AsmFuncs.nasm
View File

@ -1,7 +1,7 @@
;/** @file ;/** @file
; Low level x64 routines used by the debug support driver. ; Low level x64 routines used by the debug support driver.
; ;
; Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>
; SPDX-License-Identifier: BSD-2-Clause-Patent ; SPDX-License-Identifier: BSD-2-Clause-Patent
; ;
;**/ ;**/
@ -26,21 +26,6 @@
%define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags %define FXSTOR_FLAG 0x1000000 ; bit cpuid 24 of feature flags
;; The FXSTOR and FXRSTOR commands are used for saving and restoring the x87,
;; MMX, SSE, SSE2, etc registers. The initialization of the debugsupport driver
;; MUST check the CPUID feature flags to see that these instructions are available
;; and fail to init if they are not.
;; fxstor [rdi]
%macro FXSTOR_RDI 0
db 0xf, 0xae, 00000111y ; mod = 00, reg/op = 000, r/m = 111 = [rdi]
%endmacro
;; fxrstor [rsi]
%macro FXRSTOR_RSI 0
db 0xf, 0xae, 00001110y ; mod = 00, reg/op = 001, r/m = 110 = [rsi]
%endmacro
SECTION .data SECTION .data
global ASM_PFX(OrigVector) global ASM_PFX(OrigVector)
@ -381,7 +366,7 @@ ExtraPushDone:
; IMPORTANT!! The debug stack has been carefully constructed to ; IMPORTANT!! The debug stack has been carefully constructed to
; insure that rsp and rdi are 16 byte aligned when we get here. ; insure that rsp and rdi are 16 byte aligned when we get here.
; They MUST be. If they are not, a GP fault will occur. ; They MUST be. If they are not, a GP fault will occur.
FXSTOR_RDI fxsave [rdi]
;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear ;; UEFI calling convention for x64 requires that Direction flag in EFLAGs is clear
cld cld
@ -404,7 +389,7 @@ ExtraPushDone:
;; FX_SAVE_STATE_X64 FxSaveState; ;; FX_SAVE_STATE_X64 FxSaveState;
mov rsi, rsp mov rsi, rsp
FXRSTOR_RSI fxrstor [rsi]
add rsp, 512 add rsp, 512
;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7; ;; UINT64 Dr0, Dr1, Dr2, Dr3, Dr6, Dr7;