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SysCall/AARCH64: Enabled interrupts.

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This commit is contained in:
Mikhail Krichanov 2024-05-29 14:35:33 +03:00
parent 8af0fd53c1
commit 8439ad67b4
1 changed files with 7 additions and 10 deletions
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17
MdeModulePkg/Core/Dxe/SysCall/AARCH64/CoreBootServices.S
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@ -71,7 +71,7 @@ call:
ASM_FUNC(ArmCallRing3) ASM_FUNC(ArmCallRing3)
// Save FP and LR on Core Stack. // Save FP and LR on Core Stack.
stp x29, x30, [sp, #-0x10]! stp x29, x30, [sp, #-0x10]!
// Disable interrupts // Disable interrupts.
msr daifset, #0xf msr daifset, #0xf
isb isb
// Prepare Ring3 SP and EntryPoint. // Prepare Ring3 SP and EntryPoint.
@ -81,13 +81,10 @@ ASM_FUNC(ArmCallRing3)
mov x5, sp mov x5, sp
str x5, [x4] str x5, [x4]
mov sp, x3 mov sp, x3
// Copy PSTATE to SPSR. // Copy PSTATE to SPSR.
mrs x1, nzcv mrs x1, nzcv
mrs x2, pan mrs x2, pan
orr x1, x1, x2 orr x1, x1, x2
mrs x2, daif
orr x1, x1, x2
// //
// M[3:0], bits [3:0] AArch64 Exception level and selected Stack Pointer. // M[3:0], bits [3:0] AArch64 Exception level and selected Stack Pointer.
// 0b0000 - EL0. // 0b0000 - EL0.
@ -95,10 +92,8 @@ ASM_FUNC(ArmCallRing3)
// 0b0101 - EL1 with SP_EL1 (EL1h). // 0b0101 - EL1 with SP_EL1 (EL1h).
// //
msr spsr_el1, x1 msr spsr_el1, x1
isb isb
dsb sy dsb sy
eret eret
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
@ -110,14 +105,16 @@ ASM_FUNC(ArmCallRing3)
// ); // );
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------
ASM_FUNC(ReturnToCore) ASM_FUNC(ReturnToCore)
// Zero Exception Syndrome Register to prevent QEMU from random crashing.
msr esr_el1, xzr
// Switch to Core Stack. // Switch to Core Stack.
mov sp, x1 mov sp, x1
// Zero Exception Syndrome Register to prevent QEMU from random crashing.
mov x1, #0
msr esr_el1, x1
// Restore Stack. // Restore Stack.
ldp x29, x30, [sp] ldp x29, x30, [sp]
add sp, sp, #0x10 add sp, sp, #0x10
// Enable interrupts.
msr daifclr, #0xf
isb
ret ret
//------------------------------------------------------------------------------ //------------------------------------------------------------------------------