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UefiCpuPkg/MpLib.c: Add checking CR0 PG bit 

If CR0 PG bit is not set, it means paging is not enabled on BSP. Thus, Execute
Disable feature is not working actually. Thus, we cannot enable it on APs.

v2:
  Correct the commit log.

Cc: Feng Tian <feng.tian@intel.com>
Cc: Michael Kinney <michael.d.kinney@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jeff Fan <jeff.fan@intel.com>
Reviewed-by: Feng Tian <feng.tian@intel.com>
This commit is contained in:
Jeff Fan 2017-03-27 15:00:00 +08:00
parent 98eb009563
commit 844b2d072d
1 changed files with 24 additions and 14 deletions
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38
UefiCpuPkg/Library/MpInitLib/MpLib.c
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@ -1,7 +1,7 @@
/** @file /** @file
CPU MP Initialize Library common functions. CPU MP Initialize Library common functions.
Copyright (c) 2016, Intel Corporation. All rights reserved.<BR> Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -18,8 +18,11 @@ EFI_GUID mCpuInitMpLibHobGuid = CPU_INIT_MP_LIB_HOB_GUID;
/** /**
The function will check if BSP Execute Disable is enabled. The function will check if BSP Execute Disable is enabled.
DxeIpl may have enabled Execute Disable for BSP,
APs need to get the status and sync up the settings. DxeIpl may have enabled Execute Disable for BSP, APs need to
get the status and sync up the settings.
If BSP's CR0.Paging is not set, BSP execute Disble feature is
not working actually.
@retval TRUE BSP Execute Disable is enabled. @retval TRUE BSP Execute Disable is enabled.
@retval FALSE BSP Execute Disable is not enabled. @retval FALSE BSP Execute Disable is not enabled.
@ -33,23 +36,30 @@ IsBspExecuteDisableEnabled (
CPUID_EXTENDED_CPU_SIG_EDX Edx; CPUID_EXTENDED_CPU_SIG_EDX Edx;
MSR_IA32_EFER_REGISTER EferMsr; MSR_IA32_EFER_REGISTER EferMsr;
BOOLEAN Enabled; BOOLEAN Enabled;
IA32_CR0 Cr0;
Enabled = FALSE; Enabled = FALSE;
AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL); Cr0.UintN = AsmReadCr0 ();
if (Eax >= CPUID_EXTENDED_CPU_SIG) { if (Cr0.Bits.PG != 0) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32);
// //
// CPUID 0x80000001 // If CR0 Paging bit is set
// Bit 20: Execute Disable Bit available.
// //
if (Edx.Bits.NX != 0) { AsmCpuid (CPUID_EXTENDED_FUNCTION, &Eax, NULL, NULL, NULL);
EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER); if (Eax >= CPUID_EXTENDED_CPU_SIG) {
AsmCpuid (CPUID_EXTENDED_CPU_SIG, NULL, NULL, NULL, &Edx.Uint32);
// //
// MSR 0xC0000080 // CPUID 0x80000001
// Bit 11: Execute Disable Bit enable. // Bit 20: Execute Disable Bit available.
// //
if (EferMsr.Bits.NXE != 0) { if (Edx.Bits.NX != 0) {
Enabled = TRUE; EferMsr.Uint64 = AsmReadMsr64 (MSR_IA32_EFER);
//
// MSR 0xC0000080
// Bit 11: Execute Disable Bit enable.
//
if (EferMsr.Bits.NXE != 0) {
Enabled = TRUE;
}
} }
} }
} }