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UefiCpuPkg/PiSmmCpuDxeSmm: Replace mIsBsp by mBspApicId check 

This patch is to replace mIsBsp by mBspApicId check.
mIsBsp becomes the local variable (IsBsp), then it can be
checked dynamically in the function. Instead, we define the
mBspApicId, which is to record the BSP ApicId used for
compare in SmmInitHandler. With this change, SmmInitHandler
can be run in parallel during SMM init.

Note:
This patch is the per-prepared work by refining the
SmmInitHandler, then, we can do the next step to
combine 2 SMIs (gcSmmInitTemplate & gcSmiHandlerTemplate)
into one (gcSmiHandlerTemplate), the new SMI handler
will call the SmmInitHandler in parallel to do the init.

Cc: Eric Dong <eric.dong@intel.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Zeng Star <star.zeng@intel.com>
Cc: Laszlo Ersek <lersek@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: Rahul Kumar <rahul1.kumar@intel.com>
Signed-off-by: Jiaxin Wu <jiaxin.wu@intel.com>
Reviewed-by: Ray Ni <ray.ni@intel.com>
Reviewed-by: Gerd Hoffmann <kraxel@redhat.com>
This commit is contained in:
Wu, Jiaxin 2023-02-16 14:16:29 +08:00 committed by mergify[bot]
parent cb4820b6c1
commit 85c6c14c4c
1 changed files with 12 additions and 11 deletions
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23
UefiCpuPkg/PiSmmCpuDxeSmm/PiSmmCpuDxeSmm.c
View File

@ -59,7 +59,6 @@ SMM_CPU_PRIVATE_DATA *gSmmCpuPrivate = &mSmmCpuPrivateData;
// SMM Relocation variables
//
volatile BOOLEAN *mRebased;
volatile BOOLEAN mIsBsp;
///
/// Handle for the SMM CPU Protocol
@ -85,6 +84,8 @@ EDKII_SMM_MEMORY_ATTRIBUTE_PROTOCOL mSmmMemoryAttribute = {
EFI_CPU_INTERRUPT_HANDLER mExternalVectorTable[EXCEPTION_VECTOR_NUMBER];
UINT32 mBspApicId = 0;
//
// SMM stack information
//
@ -343,8 +344,9 @@ SmmInitHandler (
VOID
)
{
UINT32 ApicId;
UINTN Index;
UINT32 ApicId;
UINTN Index;
BOOLEAN IsBsp;
//
// Update SMM IDT entries' code segment and load IDT
@ -352,6 +354,8 @@ SmmInitHandler (
AsmWriteIdtr (&gcSmiIdtr);
ApicId = GetApicId ();
IsBsp = (BOOLEAN)(mBspApicId == ApicId);
ASSERT (mNumberOfCpus <= mMaxNumberOfCpus);
for (Index = 0; Index < mNumberOfCpus; Index++) {
@ -361,7 +365,7 @@ SmmInitHandler (
//
SmmCpuFeaturesInitializeProcessor (
Index,
mIsBsp,
IsBsp,
gSmmCpuPrivate->ProcessorInfo,
&mCpuHotPlugData
);
@ -371,7 +375,7 @@ SmmInitHandler (
// Check XD and BTS features on each processor on normal boot
//
CheckFeatureSupported ();
} else if (mIsBsp) {
} else if (IsBsp) {
//
// BSP rebase is already done above.
// Initialize private data during S3 resume
@ -407,7 +411,6 @@ SmmRelocateBases (
SMRAM_SAVE_STATE_MAP BakBuf2;
SMRAM_SAVE_STATE_MAP *CpuStatePtr;
UINT8 *U8Ptr;
UINT32 ApicId;
UINTN Index;
UINTN BspIndex;
@ -448,17 +451,16 @@ SmmRelocateBases (
//
// Retrieve the local APIC ID of current processor
//
ApicId = GetApicId ();
mBspApicId = GetApicId ();
//
// Relocate SM bases for all APs
// This is APs' 1st SMI - rebase will be done here, and APs' default SMI handler will be overridden by gcSmmInitTemplate
//
mIsBsp = FALSE;
BspIndex = (UINTN)-1;
for (Index = 0; Index < mNumberOfCpus; Index++) {
mRebased[Index] = FALSE;
if (ApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
if (mBspApicId != (UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId) {
SendSmiIpi ((UINT32)gSmmCpuPrivate->ProcessorInfo[Index].ProcessorId);
//
// Wait for this AP to finish its 1st SMI
@ -477,8 +479,7 @@ SmmRelocateBases (
// Relocate BSP's SMM base
//
ASSERT (BspIndex != (UINTN)-1);
mIsBsp = TRUE;
SendSmiIpi (ApicId);
SendSmiIpi (mBspApicId);
//
// Wait for the BSP to finish its 1st SMI
//