mirror of https://github.com/acidanthera/audk.git
Do not update the GL-GD5446 DRAM Control register during
InitializeGraphicsMode. The update of this register would cause the xorg-cirrus driver to mis-detect the size of video memory for the QEMU cirrus video device. git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@8690 6f19259b-4bc3-4df7-8a09-765794883524
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@ -770,6 +770,20 @@ InitializeGraphicsMode (
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{
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UINT8 Byte;
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UINTN Index;
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UINT16 DeviceId;
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//
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// Read the PCI Configuration Header from the PCI Device
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//
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ASSERT_EFI_ERROR (
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Private->PciIo->Pci.Read (
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Private->PciIo,
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EfiPciIoWidthUint16,
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PCI_DEVICE_ID_OFFSET,
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1,
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&DeviceId
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)
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);
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outw (Private, SEQ_ADDRESS_REGISTER, 0x1206);
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outw (Private, SEQ_ADDRESS_REGISTER, 0x0012);
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@ -778,9 +792,11 @@ InitializeGraphicsMode (
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outw (Private, SEQ_ADDRESS_REGISTER, ModeData->SeqSettings[Index]);
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}
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outb (Private, SEQ_ADDRESS_REGISTER, 0x0f);
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Byte = (UINT8) ((inb (Private, SEQ_DATA_REGISTER) & 0xc7) ^ 0x30);
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outb (Private, SEQ_DATA_REGISTER, Byte);
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if (DeviceId != CIRRUS_LOGIC_5446_DEVICE_ID) {
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outb (Private, SEQ_ADDRESS_REGISTER, 0x0f);
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Byte = (UINT8) ((inb (Private, SEQ_DATA_REGISTER) & 0xc7) ^ 0x30);
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outb (Private, SEQ_DATA_REGISTER, Byte);
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}
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outb (Private, MISC_OUTPUT_REGISTER, ModeData->MiscSetting);
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outw (Private, GRAPH_ADDRESS_REGISTER, 0x0506);
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