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MdePkg: Add PCI Express 6.0 Header Support

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PCI Express 6.0 Specification introduces new registers and modifies
fields in existing ones.

This commit syncs PciE headers with the spec update.

Cc: Sergiy Yakovlev <sergiyy@ami.com>
Cc: Felix Polyudov <felixp@ami.com>
Cc: Dhanaraj V <vdhanaraj@ami.com>
Cc: Ray Ni <ray.ni@intel.com>
Cc: Liming Gao <gaoliming@byosoft.com.cn>
Signed-off-by: Sachin Ganesh <sachinganesh@ami.com>
This commit is contained in:
Sachin Ganesh 2024-07-19 14:26:47 +05:30 committed by mergify[bot]
parent 7e5a5ae154
commit 85fad9912c
3 changed files with 173 additions and 22 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
MdePkg/Include/IndustryStandard/Pci.h
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@ -9,7 +9,7 @@ SPDX-License-Identifier: BSD-2-Clause-Patent
#ifndef _PCI_H_
#define _PCI_H_
#include <IndustryStandard/PciExpress50.h>
#include <IndustryStandard/PciExpress60.h>
#include <IndustryStandard/PciCodeId.h>
#endif

72
MdePkg/Include/IndustryStandard/PciExpress21.h
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@ -40,7 +40,7 @@ typedef union {
UINT16 SlotImplemented : 1;
UINT16 InterruptMessageNumber : 5;
UINT16 Undefined : 1;
UINT16 Reserved : 1;
UINT16 FlitModeSupported : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_CAPABILITY;
@ -64,11 +64,13 @@ typedef union {
UINT32 EndpointL1AcceptableLatency : 3;
UINT32 Undefined : 3;
UINT32 RoleBasedErrorReporting : 1;
UINT32 Reserved : 2;
UINT32 ErrCorSubclassCapable : 1;
UINT32 RxMpsFixed : 1;
UINT32 CapturedSlotPowerLimitValue : 8;
UINT32 CapturedSlotPowerLimitScale : 2;
UINT32 FunctionLevelReset : 1;
UINT32 Reserved2 : 3;
UINT32 MixedMpsSupported : 1;
UINT32 Reserved2 : 2;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY;
@ -111,13 +113,14 @@ typedef union {
typedef union {
struct {
UINT16 CorrectableError : 1;
UINT16 NonFatalError : 1;
UINT16 FatalError : 1;
UINT16 UnsupportedRequest : 1;
UINT16 AuxPower : 1;
UINT16 TransactionsPending : 1;
UINT16 Reserved : 10;
UINT16 CorrectableError : 1;
UINT16 NonFatalError : 1;
UINT16 FatalError : 1;
UINT16 UnsupportedRequest : 1;
UINT16 AuxPower : 1;
UINT16 TransactionsPending : 1;
UINT16 EmergencyPowerReductionDetected : 1;
UINT16 Reserved : 9;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_DEVICE_STATUS;
@ -146,7 +149,7 @@ typedef union {
typedef union {
struct {
UINT16 AspmControl : 2;
UINT16 Reserved : 1;
UINT16 PtmPropagationDelayB : 1;
UINT16 ReadCompletionBoundary : 1;
UINT16 LinkDisable : 1;
UINT16 RetrainLink : 1;
@ -156,6 +159,9 @@ typedef union {
UINT16 HardwareAutonomousWidthDisable : 1;
UINT16 LinkBandwidthManagementInterrupt : 1;
UINT16 LinkAutonomousBandwidthInterrupt : 1;
UINT16 SrisClocking : 1;
UINT16 FlitModeDisable : 1;
UINT16 DrsSignalingControl : 2;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_CONTROL;
@ -205,7 +211,9 @@ typedef union {
UINT16 PowerController : 1;
UINT16 ElectromechanicalInterlock : 1;
UINT16 DataLinkLayerStateChanged : 1;
UINT16 Reserved : 3;
UINT16 AutoSlotPowerLimitDisable : 1;
UINT16 InbandPdDisable : 1;
UINT16 Reserved : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_SLOT_CONTROL;
@ -233,7 +241,8 @@ typedef union {
UINT16 SystemErrorOnFatalError : 1;
UINT16 PmeInterrupt : 1;
UINT16 CrsSoftwareVisibility : 1;
UINT16 Reserved : 11;
UINT16 NoNfmSubtree : 1;
UINT16 Reserved : 10;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_ROOT_CONTROL;
@ -268,7 +277,7 @@ typedef union {
UINT32 NoRoEnabledPrPrPassing : 1;
UINT32 LtrMechanism : 1;
UINT32 TphCompleter : 2;
UINT32 LnSystemCLS : 2;
UINT32 Reserved : 2;
UINT32 TenBitTagCompleterSupported : 1;
UINT32 TenBitTagRequesterSupported : 1;
UINT32 Obff : 2;
@ -277,7 +286,9 @@ typedef union {
UINT32 MaxEndEndTlpPrefixes : 2;
UINT32 EmergencyPowerReductionSupported : 2;
UINT32 EmergencyPowerReductionInitializationRequired : 1;
UINT32 Reserved3 : 4;
UINT32 Reserved2 : 1;
UINT32 DmwrCompleter : 1;
UINT32 DmwrLengths : 2;
UINT32 FrsSupported : 1;
} Bits;
UINT32 Uint32;
@ -330,10 +341,15 @@ typedef union {
typedef union {
struct {
UINT32 Reserved : 1;
UINT32 LinkSpeedsVector : 7;
UINT32 Crosslink : 1;
UINT32 Reserved2 : 23;
UINT32 Reserved : 1;
UINT32 LinkSpeedsVector : 7;
UINT32 Crosslink : 1;
UINT32 LowerSkpOsGeneration : 7;
UINT32 LowerSkpOsReception : 7;
UINT32 RetimerPresenceDetect : 1;
UINT32 TwoRetimersPresenceDetect : 1;
UINT32 Reserved2 : 6;
UINT32 DrsSupported : 1;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_LINK_CAPABILITY2;
@ -360,11 +376,25 @@ typedef union {
UINT16 EqualizationPhase2Successful : 1;
UINT16 EqualizationPhase3Successful : 1;
UINT16 LinkEqualizationRequest : 1;
UINT16 Reserved : 10;
UINT16 RetimerPresence : 1;
UINT16 TwoRetimersPresence : 1;
UINT16 CrosslinkResolution : 2;
UINT16 FlitModeStatus : 1;
UINT16 Reserved : 1;
UINT16 DownstreamComponentPresence : 3;
UINT16 DRSMessageReceived : 1;
} Bits;
UINT16 Uint16;
} PCI_REG_PCIE_LINK_STATUS2;
typedef union {
struct {
UINT32 InbandPdDisable : 1;
UINT32 Reserved : 30;
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_SLOT_CAPABILITY2;
typedef struct {
EFI_PCI_CAPABILITY_HDR Hdr;
PCI_REG_PCIE_CAPABILITY Capability;
@ -386,7 +416,7 @@ typedef struct {
PCI_REG_PCIE_LINK_CAPABILITY2 LinkCapability2;
PCI_REG_PCIE_LINK_CONTROL2 LinkControl2;
PCI_REG_PCIE_LINK_STATUS2 LinkStatus2;
UINT32 SlotCapability2;
PCI_REG_PCIE_SLOT_CAPABILITY2 SlotCapability2;
UINT16 SlotControl2;
UINT16 SlotStatus2;
} PCI_CAPABILITY_PCIEXP;

121
MdePkg/Include/IndustryStandard/PciExpress60.h Normal file
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@ -0,0 +1,121 @@
/** @file
Support for the PCI Express 6.0 standard.
This header file may not define all structures. Please extend as required.
Copyright (c) 2024, American Megatrends International LLC. All rights reserved.<BR>
SPDX-License-Identifier: BSD-2-Clause-Patent
**/
#ifndef PCIEXPRESS60_H_
#define PCIEXPRESS60_H_
#include <IndustryStandard/PciExpress50.h>
/// The Physical Layer PCI Express Extended Capability definitions.
///
/// Based on section 7.7.7 of PCI Express Base Specification 6.0.
///@{
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_ID 0x0031
#define PCI_EXPRESS_EXTENDED_CAPABILITY_PHYSICAL_LAYER_64_0_VER1 0x1
// Register offsets from Physical Layer PCI-E Ext Cap Header
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES_OFFSET 0x04
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL_OFFSET 0x08
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS_OFFSET 0x0C
#define PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL_OFFSET 0x10
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_ID 0x002F
#define PCI_EXPRESS_EXTENDED_CAPABILITY_DEVICE3_VER1 0x1
#define EFI_PCIE_CAPABILITY_DEVICE_CAPABILITIES_3_OFFSET 0x04
#define EFI_PCIE_CAPABILITY_DEVICE_CONTROL_3_OFFSET 0x08
#define EFI_PCIE_CAPABILITY_DEVICE_STATUS_3_OFFSET 0x0C
#pragma pack(1)
typedef union {
struct {
UINT32 Reserved : 32; // Reserved bit 0:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES;
typedef union {
struct {
UINT32 Reserved : 32; // Reserved bit 0:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL;
typedef union {
struct {
UINT32 EqualizationComplete : 1; // bit 0
UINT32 EqualizationPhase1Success : 1; // bit 1
UINT32 EqualizationPhase2Success : 1; // bit 2
UINT32 EqualizationPhase3Success : 1; // bit 3
UINT32 LinkEqualizationRequest : 1; // bit 4
UINT32 TransmitterPrecodingOn : 1; // bit 5
UINT32 TransmitterPrecodeRequest : 1; // bit 6
UINT32 NoEqualizationNeededRcvd : 1; // bit 7
UINT32 Reserved : 24; // Reserved bit 8:31
} Bits;
UINT32 Uint32;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS;
typedef union {
struct {
UINT8 DownstreamPortTransmitterPreset : 4; // bit 0..3
UINT8 UpstreamPortTransmitterPreset : 4; // bit 4..7
} Bits;
UINT8 Uint8;
} PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL;
typedef struct {
PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header;
PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CAPABILITIES Capablities;
PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_CONTROL Control;
PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_STATUS Status;
PCI_EXPRESS_REG_PHYSICAL_LAYER_64_0_LANE_EQUALIZATION_CONTROL LaneEqualizationControl[1];
} PCI_EXPRESS_EXTENDED_CAPABILITIES_PHYSICAL_LAYER_64_0;
///@}
typedef union {
struct {
UINT32 DmwrRequestRouting : 1; // bit 0
UINT32 FourteenBitTagCompleter : 1; // bit 1
UINT32 FourteenBitTagRequester : 1; // bit 2
UINT32 ReceiverL0p : 1; // bit 3
UINT32 PortL0pExitLatencyLatency : 3; // bit 4..6
UINT32 RetimerL0pExit : 3; // bit 7..9
UINT32 Reserved : 22; // bit 10..31
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CAPABILITY3;
typedef union {
struct {
UINT32 DmwrRequesterEnable : 1; // bit 0
UINT32 DmwrEgressBlocking : 1; // bit 1
UINT32 FourteenBitTagRequesterEnable : 1; // bit 2
UINT32 L0pEnable : 1; // bit 3
UINT32 TargetLinkWidth : 3; // bit 4..6
UINT32 Reserved : 25; // bit 7..31
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_CONTROL3;
typedef union {
struct {
UINT32 InitialLinkWidth : 3; // bit 0..2
UINT32 SegmentCaptured : 1; // bit 3
UINT32 RemoteL0pSupported : 1; // bit 4
UINT32 Reserved : 27; // bit 5..31
} Bits;
UINT32 Uint32;
} PCI_REG_PCIE_DEVICE_STATUS3;
#pragma pack()
#endif