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UefiCpuPkg: Combine branch for non-present and leaf ParentEntry
Combine 'if' condition branch for non-present and leaf Parent Entry in PageTableLibMapInLevel. Most steps of these two condition are the same. This commit doesn't change any functionality. Signed-off-by: Dun Tan <dun.tan@intel.com> Cc: Eric Dong <eric.dong@intel.com> Reviewed-by: Ray Ni <ray.ni@intel.com> Cc: Rahul Kumar <rahul1.kumar@intel.com> Tested-by: Gerd Hoffmann <kraxel@redhat.com> Acked-by: Gerd Hoffmann <kraxel@redhat.com>
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@ -351,68 +351,45 @@ PageTableLibMapInLevel (
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// ParentPagingEntry ONLY is deferenced for checking Present and MustBeOne bits
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// when Modify is FALSE.
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//
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if (ParentPagingEntry->Pce.Present == 0) {
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if ((ParentPagingEntry->Pce.Present == 0) || IsPle (ParentPagingEntry, Level + 1)) {
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//
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// [LinearAddress, LinearAddress + Length] contains non-present range.
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//
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Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask);
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if (RETURN_ERROR (Status)) {
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return Status;
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}
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//
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// Check the attribute in ParentPagingEntry is equal to attribute calculated by input Attribue and Mask.
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//
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PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute);
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if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))
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== (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))
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{
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return RETURN_SUCCESS;
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}
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//
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// The parent entry is CR3 or PML5E/PML4E/PDPTE/PDE.
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// When ParentPagingEntry is non-present, parent entry is CR3 or PML5E/PML4E/PDPTE/PDE.
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// It does NOT point to an existing page directory.
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//
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ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB);
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CreateNew = TRUE;
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*BufferSize -= SIZE_4KB;
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if (Modify) {
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ParentPagingEntry->Uintn = (UINTN)Buffer + *BufferSize;
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ZeroMem ((VOID *)ParentPagingEntry->Uintn, SIZE_4KB);
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//
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// Set default attribute bits for PML5E/PML4E/PDPTE/PDE.
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//
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PageTableLibSetPnle (&ParentPagingEntry->Pnle, &NopAttribute, &AllOneMask);
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} else {
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//
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// Just make sure Present and MustBeZero (PageSize) bits are accurate.
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//
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OneOfPagingEntry.Pnle.Uint64 = 0;
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}
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} else if (IsPle (ParentPagingEntry, Level + 1)) {
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//
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// The parent entry is a PDPTE_1G or PDE_2M. Split to 2M or 4K pages.
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// When ParentPagingEntry is present, parent entry is leaf PDPTE_1G or PDE_2M. Split to 2M or 4K pages.
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// Note: it's impossible the parent entry is a PTE_4K.
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//
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//
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// Use NOP attributes as the attribute of grand-parents because CPU will consider
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// the actual attributes of grand-parents when determing the memory type.
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//
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PleBAttribute.Uint64 = PageTableLibGetPleBMapAttribute (&ParentPagingEntry->PleB, ParentAttribute);
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if (ParentPagingEntry->Pce.Present == 0) {
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//
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// [LinearAddress, LinearAddress + Length] contains non-present range.
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//
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Status = IsAttributesAndMaskValidForNonPresentEntry (Attribute, Mask);
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if (RETURN_ERROR (Status)) {
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return Status;
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}
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OneOfPagingEntry.Pnle.Uint64 = 0;
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} else {
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PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllOneMask);
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}
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//
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// Check if the attribute, the physical address calculated by ParentPagingEntry is equal to
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// the attribute, the physical address calculated by input Attribue and Mask.
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//
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if ((IA32_MAP_ATTRIBUTE_ATTRIBUTES (&PleBAttribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask))
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== (IA32_MAP_ATTRIBUTE_ATTRIBUTES (Attribute) & IA32_MAP_ATTRIBUTE_ATTRIBUTES (Mask)))
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{
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//
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// This function is called when the memory length is less than the region length of the parent level.
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// No need to split the page when the attributes equal.
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//
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if ((Mask->Bits.PageTableBaseAddressLow == 0) && (Mask->Bits.PageTableBaseAddressHigh == 0)) {
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return RETURN_SUCCESS;
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}
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//
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// Non-present entry won't reach there since:
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// 1.When map non-present entry to present, the attribute must be different.
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// 2.When still map non-present entry to non-present, PageTableBaseAddressLow and High in Mask must be 0.
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//
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ASSERT (ParentPagingEntry->Pce.Present == 1);
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PhysicalAddrInEntry = IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (&PleBAttribute) + MultU64x32 (RegionLength, (UINT32)PagingEntryIndex);
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PhysicalAddrInAttr = (IA32_MAP_ATTRIBUTE_PAGE_TABLE_BASE_ADDRESS (Attribute) + Offset) & (~RegionMask);
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if (PhysicalAddrInEntry == PhysicalAddrInAttr) {
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@ -423,17 +400,19 @@ PageTableLibMapInLevel (
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ASSERT (Buffer == NULL || *BufferSize >= SIZE_4KB);
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CreateNew = TRUE;
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*BufferSize -= SIZE_4KB;
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PageTableLibSetPle (Level, &OneOfPagingEntry, 0, &PleBAttribute, &AllOneMask);
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if (Modify) {
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//
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// Create 512 child-level entries that map to 2M/4K.
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//
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PagingEntry = (IA32_PAGING_ENTRY *)((UINTN)Buffer + *BufferSize);
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ZeroMem (PagingEntry, SIZE_4KB);
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for (SubOffset = 0, Index = 0; Index < 512; Index++) {
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PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset;
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SubOffset += RegionLength;
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if (ParentPagingEntry->Pce.Present) {
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//
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// Create 512 child-level entries that map to 2M/4K.
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//
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for (SubOffset = 0, Index = 0; Index < 512; Index++) {
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PagingEntry[Index].Uint64 = OneOfPagingEntry.Uint64 + SubOffset;
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SubOffset += RegionLength;
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}
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}
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//
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