tyler.durden/audk
1
0
Fork 0
mirror of https://github.com/acidanthera/audk.git synced 2025-07-31 01:24:12 +02:00
Code Issues Packages Projects Releases Wiki Activity

MdePkg/BaseLib: Support IA32 processors without CLFLUSH

Browse Source 
Use CPUID Leaf 01 to detect support for CLFLUSH instruction.  

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Michael Kinney <michael.d.kinney@intel.com>
Reviewed-by: Jordan Justen <jordan.l.justen@intel.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@17212 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Michael Kinney 2015-04-27 19:37:15 +00:00 committed by mdkinney
parent d2660fe32d
commit 881813d7a9
3 changed files with 43 additions and 5 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

13
MdePkg/Library/BaseLib/Ia32/FlushCacheLine.asm
View File

@ -1,6 +1,6 @@
;------------------------------------------------------------------------------ ;------------------------------------------------------------------------------
; ;
; Copyright (c) 2006, Intel Corporation. All rights reserved.<BR> ; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
; This program and the accompanying materials ; This program and the accompanying materials
; are licensed and made available under the terms and conditions of the BSD License ; are licensed and made available under the terms and conditions of the BSD License
; which accompanies this distribution. The full text of the license may be found at ; which accompanies this distribution. The full text of the license may be found at
@ -34,9 +34,20 @@
; ); ; );
;------------------------------------------------------------------------------ ;------------------------------------------------------------------------------
AsmFlushCacheLine PROC AsmFlushCacheLine PROC
;
; If the CPU does not support CLFLUSH instruction,
; then promote flush range to flush entire cache.
;
mov eax, 1
cpuid
mov eax, [esp + 4] mov eax, [esp + 4]
test edx, BIT19
jz @F
clflush [eax] clflush [eax]
ret ret
@@:
wbinvd
ret
AsmFlushCacheLine ENDP AsmFlushCacheLine ENDP
END END

18
MdePkg/Library/BaseLib/Ia32/FlushCacheLine.c
View File

@ -1,7 +1,7 @@
/** @file /** @file
AsmFlushCacheLine function AsmFlushCacheLine function
Copyright (c) 2006 - 2008, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
which accompanies this distribution. The full text of the license may be found at which accompanies this distribution. The full text of the license may be found at
@ -36,9 +36,23 @@ AsmFlushCacheLine (
IN VOID *LinearAddress IN VOID *LinearAddress
) )
{ {
//
// If the CPU does not support CLFLUSH instruction,
// then promote flush range to flush entire cache.
//
_asm { _asm {
mov eax, LinearAddress mov eax, 1
cpuid
test edx, BIT19
jz NoClflush
mov eax, [esp + 4]
clflush [eax] clflush [eax]
jmp Done
NoClflush:
wbinvd
Done:
} }
return LinearAddress;
} }

17
MdePkg/Library/BaseLib/Ia32/GccInline.c
View File

@ -1,7 +1,7 @@
/** @file /** @file
GCC inline implementation of BaseLib processor specific functions. GCC inline implementation of BaseLib processor specific functions.
Copyright (c) 2006 - 2010, Intel Corporation. All rights reserved.<BR> Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>
Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR> Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>
This program and the accompanying materials This program and the accompanying materials
are licensed and made available under the terms and conditions of the BSD License are licensed and made available under the terms and conditions of the BSD License
@ -1745,6 +1745,19 @@ AsmFlushCacheLine (
IN VOID *LinearAddress IN VOID *LinearAddress
) )
{ {
UINT32 RegEdx;
//
// If the CPU does not support CLFLUSH instruction,
// then promote flush range to flush entire cache.
//
AsmCpuid (0x01, NULL, NULL, NULL, &RegEdx);
if ((RegEdx & BIT19) == 0) {
__asm__ __volatile__ ("wbinvd":::"memory");
return LinearAddress;
}
__asm__ __volatile__ ( __asm__ __volatile__ (
"clflush (%0)" "clflush (%0)"
: "+a" (LinearAddress) : "+a" (LinearAddress)
@ -1752,7 +1765,7 @@ AsmFlushCacheLine (
: "memory" : "memory"
); );
return LinearAddress; return LinearAddress;
} }