mirror of https://github.com/acidanthera/audk.git
ARM Packages: Fixed Build failings/warnings/EDK2 coding convention
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12458 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin
parent
12fcdcb83d
commit
886f97c86b
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@ -259,7 +259,7 @@ CpuDxeInitialize (
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// If the platform is a MPCore system then install the Configuration Table describing the
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// secondary core states
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if (ArmIsMPCore()) {
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if (ArmIsMpCore()) {
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PublishArmProcessorTable();
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}
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@ -27,7 +27,7 @@ ArmGicEnableInterruptInterface (
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* Enable the CPU interface in Non-Secure world
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* Note: The ICCICR register is banked when Security extensions are implemented
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*/
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,0x00000001);
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
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}
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VOID
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@ -40,5 +40,5 @@ ArmGicEnableDistributor (
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* Enable GIC distributor in Non-Secure world.
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* Note: The ICDDCR register is banked when Security extensions are implemented
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*/
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x00000001);
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
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}
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@ -27,28 +27,31 @@ ArmGicSetupNonSecure (
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IN INTN GicInterruptInterfaceBase
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)
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{
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UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
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UINTN InterruptId;
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UINTN CachedPriorityMask;
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CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
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// Set priority Mask so that no interrupts get through to CPU
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
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// Check if there are any pending interrupts
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//TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
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while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
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while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
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// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
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UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
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// Write to End of interrupt signal
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
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}
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// Ensure all GIC interrupts are Non-Secure
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
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// Ensure all interrupts can get through the priority mask
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
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}
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VOID
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@ -57,14 +60,13 @@ ArmGicEnableInterruptInterface (
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IN INTN GicInterruptInterfaceBase
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)
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{
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */
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// Set Priority Mask to allow interrupts
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
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/*
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* Enable CPU interface in Secure world
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* Enable CPU inteface in Non-secure World
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* Signal Secure Interrupts to CPU using FIQ line *
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*/
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MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,
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// Enable CPU interface in Secure world
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// Enable CPU inteface in Non-secure World
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// Signal Secure Interrupts to CPU using FIQ line *
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MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
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ARM_GIC_ICCICR_ENABLE_SECURE |
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ARM_GIC_ICCICR_ENABLE_NS |
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ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
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@ -76,5 +78,6 @@ ArmGicEnableDistributor (
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IN INTN GicDistributorBase
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)
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{
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MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1); // turn on the GIC distributor
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// Turn on the GIC distributor
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MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
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}
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@ -97,7 +97,6 @@
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# BDS Libraries
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BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
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FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
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[LibraryClasses.common.SEC]
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DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
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@ -171,9 +171,13 @@ READ_LOCK_STATUS = TRUE
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INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
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#
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# Semi-hosting filesystem
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!if $(EDK2_ARMVE_STANDALONE) != 1
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#
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# Semi-hosting filesystem (Required the Hardware Debugger to be connected)
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#
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INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
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!endif
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#
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# FAT filesystem + GPT/MBR partitioning
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@ -194,6 +198,10 @@ READ_LOCK_STATUS = TRUE
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#
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INF EmbeddedPkg/Ebl/Ebl.inf
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!if $(EDK2_ARMVE_UEFI2_SHELL) == 1
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INF ShellPkg/Application/Shell/Shell.inf
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!endif
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#
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# Bds
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#
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@ -278,7 +278,6 @@
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# Application
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#
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EmbeddedPkg/Ebl/Ebl.inf
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ArmPkg/Application/VariableServicesTest/VariableServicesTest.inf
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!ifdef $(EDK2_ARMVE_UEFI2_SHELL)
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ShellPkg/Application/Shell/Shell.inf {
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@ -156,32 +156,14 @@ READ_LOCK_STATUS = TRUE
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INF FatPkg/EnhancedFatDxe/Fat.inf
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INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
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#
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# Multimedia Card Interface
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#
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INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
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INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
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#
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# UEFI application (Shell Embedded Boot Loader)
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#
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INF EmbeddedPkg/Ebl/Ebl.inf
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#
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# UEFI application (Full EFI Shell)
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#
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FILE APPLICATION = PCD(gArmTokenSpaceGuid.PcdShellFile) {
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SECTION PE32 = EdkShellBinPkg/FullShell/Arm/ShellFull.efi
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SECTION UI = "ShellFull"
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}
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!if $(EDK2_ARMVE_UEFI2_SHELL) == 1
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INF ShellPkg/Application/Shell/Shell.inf
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!endif
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#
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# UEFI application (Test Variable Services)
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#
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INF ArmPkg/Application/VariableServicesTest/VariableServicesTest.inf
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#
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# Bds
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@ -99,7 +99,6 @@
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# BDS Libraries
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BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
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FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
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[LibraryClasses.common.SEC]
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DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf
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@ -70,6 +70,7 @@
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#define ARM_VE_SCC_BASE
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// SP810 Controller
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#undef SP810_CTRL_BASE
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#define SP810_CTRL_BASE 0x1C020000
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// PL111 Colour LCD Controller
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@ -21,7 +21,7 @@
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#include <Library/PrintLib.h>
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#include <Library/SerialPortLib.h>
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#include <Chipset/ArmV7.h>
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#include <Chipset/ArmV7.h>
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// When the firmware is built as not Standalone, the secondary cores need to wait the firmware
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// entirely written into DRAM. It is the firmware from DRAM which will wake up the secondary cores.
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@ -120,7 +120,7 @@ EblSymbolTable (
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@param Argc Number of command arguments in Argv
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@param Argv Array of strings that represent the parsed command line.
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Argv[0] is the comamnd name
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Argv[0] is the command name
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@return EFI_SUCCESS
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@ -202,7 +202,7 @@ STATIC CHAR8 *mTokenList[] = {
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@param Argc Number of command arguments in Argv
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@param Argv Array of strings that represent the parsed command line.
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Argv[0] is the comamnd name
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Argv[0] is the command name
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@return EFI_SUCCESS
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@ -21,7 +21,7 @@
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GCC_ASM_IMPORT(CEntryPoint)
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GCC_ASM_IMPORT(ArmReadMpidr)
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GCC_ASM_IMPORT(ArmIsMPCore)
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GCC_ASM_IMPORT(ArmIsMpCore)
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GCC_ASM_EXPORT(_ModuleEntryPoint)
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StartupAddr: .word CEntryPoint
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@ -77,7 +77,7 @@ _SetupStack:
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_GetStackBase:
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// Compute Base of Normal stacks for CPU Cores
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// Is it MpCore system
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bl ArmIsMPCore
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bl ArmIsMpCore
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cmp r0, #0
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// Case it is not an MP Core system. Just setup the primary core
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beq _SetupUnicoreStack
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@ -20,7 +20,7 @@
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IMPORT CEntryPoint
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IMPORT ArmReadMpidr
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IMPORT ArmIsMPCore
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IMPORT ArmIsMpCore
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EXPORT _ModuleEntryPoint
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PRESERVE8
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@ -78,7 +78,7 @@ _SetupStack
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_GetStackBase
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// Compute Base of Normal stacks for CPU Cores
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// Is it MpCore system
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bl ArmIsMPCore
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bl ArmIsMpCore
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cmp r0, #0
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// Case it is not an MP Core system. Just setup the primary core
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beq _SetupUnicoreStack
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@ -61,11 +61,5 @@
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gEfiUsbIoProtocolGuid
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gEfiFirmwareVolume2ProtocolGuid
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[FeaturePcd]
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[FixedPcd]
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gEmbeddedTokenSpaceGuid.PcdPrePiStackSize
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[Depex]
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TRUE
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@ -122,7 +122,6 @@
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DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
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BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
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FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
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[LibraryClasses.common.SEC]
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
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@ -175,7 +174,6 @@
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SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
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PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
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[LibraryClasses.common.UEFI_APPLICATION]
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ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
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UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
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@ -207,18 +205,11 @@
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[BuildOptions]
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XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7
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XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7
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XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7
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XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
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XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
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GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb
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GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a
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GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
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GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
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RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8 --thumb
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RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
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RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
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RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8
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################################################################################
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#
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@ -309,9 +300,6 @@
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gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
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gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
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gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0
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gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0
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#
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# Optional feature to help prevent EFI memory map fragments
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# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
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@ -347,17 +335,6 @@
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# Size of the region reserved for fixed address allocations (Reserved 32MB)
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gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x02000000
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# Reserved to store the HobBase address (top of UEFI Memory Region)
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# = (PcdSystemMemoryBase + PcdSystemMemorySize) - sizeof(UINT32)
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gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x87FFFFFC
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#gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000
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gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory
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gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack
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gEmbeddedTokenSpaceGuid.PcdMemoryBase|0x80000000
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gEmbeddedTokenSpaceGuid.PcdMemorySize|0x10000000
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gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80008000
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gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
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@ -392,14 +369,14 @@
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################################################################################
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[Components.common]
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#
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# SEC
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#
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#
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# SEC
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#
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ArmPlatformPkg/PrePi/PeiUniCore.inf
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#
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# DXE
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#
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#
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# DXE
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#
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MdeModulePkg/Core/Dxe/DxeMain.inf {
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<LibraryClasses>
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PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf
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@ -122,7 +122,6 @@
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DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
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BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
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FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
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[LibraryClasses.common.SEC]
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ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
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@ -202,18 +201,11 @@
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[BuildOptions]
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XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7
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XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7
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XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7
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XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
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XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
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GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb
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GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a
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GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
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GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
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RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8 --thumb
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RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
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RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
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RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8
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################################################################################
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#
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@ -174,7 +174,6 @@ READ_LOCK_STATUS = TRUE
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INF ArmPlatformPkg/Bds/Bds.inf
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[FV.FVMAIN_COMPACT]
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FvAlignment = 8
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ERASE_POLARITY = 1
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|
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@ -125,7 +125,7 @@ LibResetSystem (
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switch (ResetType) {
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case EfiResetWarm:
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//Perform warm reset of the system by jumping to the begining of the FV
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StartOfFv = (CALL_STUB)(UINTN)PcdGet32(PcdFlashFvMainBase);
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StartOfFv = (CALL_STUB)(UINTN)PcdGet32(PcdFvBaseAddress);
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StartOfFv ();
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break;
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case EfiResetCold:
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@ -46,4 +46,4 @@
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UefiBootServicesTableLib
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[Pcd]
|
||||
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase
|
||||
gArmTokenSpaceGuid.PcdFvBaseAddress
|
||||
|
|
|
|||
|
|
@ -32,7 +32,7 @@ SET TARGET=DEBUG
|
|||
SET BUILD_ROOT=%WORKSPACE%\Build\BeagleBoard\%TARGET%_%TARGET_TOOLS%
|
||||
|
||||
@REM Build the Beagle Board firmware and creat an FD (FLASH Device) Image.
|
||||
CALL build -p BeagleBoardPkg\BeagleBoardPkg.dsc -a ARM -t RVCT31 -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8
|
||||
CALL build -p BeagleBoardPkg\BeagleBoardPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8
|
||||
@if ERRORLEVEL 1 goto Exit
|
||||
|
||||
@if /I "%1"=="CLEAN" goto Clean
|
||||
|
|
|
|||
|
|
@ -137,7 +137,7 @@ rm -f $FLASH_BOOT
|
|||
# point looks so strange.
|
||||
# OMAP 3430 TRM section 26.4.8 has Image header information. (missing in OMAP 3530 TRM)
|
||||
#
|
||||
$GENERATE_IMAGE -D $WORKSPACE/BeagleBoardPkg/ConfigurationHeader.dat -E 0x80008208 -I $BUILD_ROOT/FV/BEAGLEBOARD_EFI.fd -O $FLASH_BOOT
|
||||
$GENERATE_IMAGE -D $WORKSPACE/BeagleBoardPkg/ConfigurationHeader.dat -E 0x80008000 -I $BUILD_ROOT/FV/BEAGLEBOARD_EFI.fd -O $FLASH_BOOT
|
||||
|
||||
echo Creating debugger scripts
|
||||
process_debug_scripts $WORKSPACE/BeagleBoardPkg/Debugger_scripts
|
||||
|
|
|
|||
Loading…
Reference in New Issue