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ARM Packages: Fixed Build failings/warnings/EDK2 coding convention

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git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@12458 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
oliviermartin 2011-09-27 16:42:47 +00:00
parent 12fcdcb83d
commit 886f97c86b
21 changed files with 56 additions and 103 deletions
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2
ArmPkg/Drivers/CpuDxe/CpuDxe.c
View File

@ -259,7 +259,7 @@ CpuDxeInitialize (
// If the platform is a MPCore system then install the Configuration Table describing the // If the platform is a MPCore system then install the Configuration Table describing the
// secondary core states // secondary core states
if (ArmIsMPCore()) { if (ArmIsMpCore()) {
PublishArmProcessorTable(); PublishArmProcessorTable();
} }

4
ArmPkg/Drivers/PL390Gic/PL390GicNonSec.c
View File

@ -27,7 +27,7 @@ ArmGicEnableInterruptInterface (
* Enable the CPU interface in Non-Secure world * Enable the CPU interface in Non-Secure world
* Note: The ICCICR register is banked when Security extensions are implemented * Note: The ICCICR register is banked when Security extensions are implemented
*/ */
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,0x00000001); MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR, 0x1);
} }
VOID VOID
@ -40,5 +40,5 @@ ArmGicEnableDistributor (
* Enable GIC distributor in Non-Secure world. * Enable GIC distributor in Non-Secure world.
* Note: The ICDDCR register is banked when Security extensions are implemented * Note: The ICDDCR register is banked when Security extensions are implemented
*/ */
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x00000001); MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 0x1);
} }

37
ArmPkg/Drivers/PL390Gic/PL390GicSec.c
View File

@ -27,28 +27,31 @@ ArmGicSetupNonSecure (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
UINTN CachedPriorityMask = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR); UINTN InterruptId;
UINTN CachedPriorityMask;
CachedPriorityMask = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR);
// Set priority Mask so that no interrupts get through to CPU // Set priority Mask so that no interrupts get through to CPU
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0); MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0);
// Check if there are any pending interrupts // Check if there are any pending interrupts
//TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration. //TODO: could be extended to take Peripheral interrupts into consideration, but at the moment only SGI's are taken into consideration.
while(0 != (MmioRead32(GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) { while(0 != (MmioRead32 (GicDistributorBase + ARM_GIC_ICDICPR) & 0xF)) {
// Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal // Some of the SGI's are still pending, read Ack register and send End of Interrupt Signal
UINTN InterruptId = MmioRead32(GicInterruptInterfaceBase + ARM_GIC_ICCIAR); InterruptId = MmioRead32 (GicInterruptInterfaceBase + ARM_GIC_ICCIAR);
// Write to End of interrupt signal // Write to End of interrupt signal
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId); MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCEIOR, InterruptId);
} }
// Ensure all GIC interrupts are Non-Secure // Ensure all GIC interrupts are Non-Secure
MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0] MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR, 0xffffffff); // IRQs 0-31 are Non-Secure : Private Peripheral Interrupt[31:16] & Software Generated Interrupt[15:0]
MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 4, 0xffffffff); // IRQs 32-63 are Non-Secure : Shared Peripheral Interrupt
MmioWrite32(GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2) MmioWrite32 (GicDistributorBase + ARM_GIC_ICDISR + 8, 0xffffffff); // And another 32 in case we're on the testchip : Shared Peripheral Interrupt (2)
// Ensure all interrupts can get through the priority mask // Ensure all interrupts can get through the priority mask
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask); MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, CachedPriorityMask);
} }
VOID VOID
@ -57,14 +60,13 @@ ArmGicEnableInterruptInterface (
IN INTN GicInterruptInterfaceBase IN INTN GicInterruptInterfaceBase
) )
{ {
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF); /* Set Priority Mask to allow interrupts */ // Set Priority Mask to allow interrupts
MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCPMR, 0x000000FF);
/* // Enable CPU interface in Secure world
* Enable CPU interface in Secure world // Enable CPU inteface in Non-secure World
* Enable CPU inteface in Non-secure World // Signal Secure Interrupts to CPU using FIQ line *
* Signal Secure Interrupts to CPU using FIQ line * MmioWrite32 (GicInterruptInterfaceBase + ARM_GIC_ICCICR,
*/
MmioWrite32(GicInterruptInterfaceBase + ARM_GIC_ICCICR,
ARM_GIC_ICCICR_ENABLE_SECURE | ARM_GIC_ICCICR_ENABLE_SECURE |
ARM_GIC_ICCICR_ENABLE_NS | ARM_GIC_ICCICR_ENABLE_NS |
ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ); ARM_GIC_ICCICR_SIGNAL_SECURE_TO_FIQ);
@ -76,5 +78,6 @@ ArmGicEnableDistributor (
IN INTN GicDistributorBase IN INTN GicDistributorBase
) )
{ {
MmioWrite32(GicDistributorBase + ARM_GIC_ICDDCR, 1); // turn on the GIC distributor // Turn on the GIC distributor
MmioWrite32 (GicDistributorBase + ARM_GIC_ICDDCR, 1);
} }

1
ArmPlatformPkg/ArmRealViewEbPkg/ArmRealViewEb.dsc.inc
View File

@ -97,7 +97,6 @@
# BDS Libraries # BDS Libraries
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
[LibraryClasses.common.SEC] [LibraryClasses.common.SEC]
DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf

10
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-CTA9x4.fdf
View File

@ -171,9 +171,13 @@ READ_LOCK_STATUS = TRUE
INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf INF ArmPlatformPkg/Drivers/SP805WatchdogDxe/SP805WatchdogDxe.inf
# #
# Semi-hosting filesystem
!if $(EDK2_ARMVE_STANDALONE) != 1
#
# Semi-hosting filesystem (Required the Hardware Debugger to be connected)
# #
INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf INF ArmPkg/Filesystem/SemihostFs/SemihostFs.inf
!endif
# #
# FAT filesystem + GPT/MBR partitioning # FAT filesystem + GPT/MBR partitioning
@ -194,6 +198,10 @@ READ_LOCK_STATUS = TRUE
# #
INF EmbeddedPkg/Ebl/Ebl.inf INF EmbeddedPkg/Ebl/Ebl.inf
!if $(EDK2_ARMVE_UEFI2_SHELL) == 1
INF ShellPkg/Application/Shell/Shell.inf
!endif
# #
# Bds # Bds
# #

1
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.dsc
View File

@ -278,7 +278,6 @@
# Application # Application
# #
EmbeddedPkg/Ebl/Ebl.inf EmbeddedPkg/Ebl/Ebl.inf
ArmPkg/Application/VariableServicesTest/VariableServicesTest.inf
!ifdef $(EDK2_ARMVE_UEFI2_SHELL) !ifdef $(EDK2_ARMVE_UEFI2_SHELL)
ShellPkg/Application/Shell/Shell.inf { ShellPkg/Application/Shell/Shell.inf {

18
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress-RTSM-A9x4.fdf
View File

@ -156,32 +156,14 @@ READ_LOCK_STATUS = TRUE
INF FatPkg/EnhancedFatDxe/Fat.inf INF FatPkg/EnhancedFatDxe/Fat.inf
INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf INF MdeModulePkg/Universal/Disk/UnicodeCollation/EnglishDxe/EnglishDxe.inf
#
# Multimedia Card Interface
#
INF EmbeddedPkg/Universal/MmcDxe/MmcDxe.inf
INF ArmPlatformPkg/Drivers/PL180MciDxe/PL180MciDxe.inf
# #
# UEFI application (Shell Embedded Boot Loader) # UEFI application (Shell Embedded Boot Loader)
# #
INF EmbeddedPkg/Ebl/Ebl.inf INF EmbeddedPkg/Ebl/Ebl.inf
#
# UEFI application (Full EFI Shell)
#
FILE APPLICATION = PCD(gArmTokenSpaceGuid.PcdShellFile) {
SECTION PE32 = EdkShellBinPkg/FullShell/Arm/ShellFull.efi
SECTION UI = "ShellFull"
}
!if $(EDK2_ARMVE_UEFI2_SHELL) == 1 !if $(EDK2_ARMVE_UEFI2_SHELL) == 1
INF ShellPkg/Application/Shell/Shell.inf INF ShellPkg/Application/Shell/Shell.inf
!endif !endif
#
# UEFI application (Test Variable Services)
#
INF ArmPkg/Application/VariableServicesTest/VariableServicesTest.inf
# #
# Bds # Bds

1
ArmPlatformPkg/ArmVExpressPkg/ArmVExpress.dsc.inc
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@ -99,7 +99,6 @@
# BDS Libraries # BDS Libraries
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
[LibraryClasses.common.SEC] [LibraryClasses.common.SEC]
DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf DebugSecExtraActionLib|ArmPlatformPkg/Library/DebugSecExtraActionLib/DebugSecExtraActionLib.inf

1
ArmPlatformPkg/ArmVExpressPkg/Include/Platform/RTSM/ArmPlatform.h
View File

@ -70,6 +70,7 @@
#define ARM_VE_SCC_BASE #define ARM_VE_SCC_BASE
// SP810 Controller // SP810 Controller
#undef SP810_CTRL_BASE
#define SP810_CTRL_BASE 0x1C020000 #define SP810_CTRL_BASE 0x1C020000
// PL111 Colour LCD Controller // PL111 Colour LCD Controller

4
ArmPlatformPkg/Library/EblCmdLib/EblCmdLib.c
View File

@ -120,7 +120,7 @@ EblSymbolTable (
@param Argc Number of command arguments in Argv @param Argc Number of command arguments in Argv
@param Argv Array of strings that represent the parsed command line. @param Argv Array of strings that represent the parsed command line.
Argv[0] is the comamnd name Argv[0] is the command name
@return EFI_SUCCESS @return EFI_SUCCESS
@ -202,7 +202,7 @@ STATIC CHAR8 *mTokenList[] = {
@param Argc Number of command arguments in Argv @param Argc Number of command arguments in Argv
@param Argv Array of strings that represent the parsed command line. @param Argv Array of strings that represent the parsed command line.
Argv[0] is the comamnd name Argv[0] is the command name
@return EFI_SUCCESS @return EFI_SUCCESS

4
ArmPlatformPkg/PrePi/ModuleEntryPoint.S
View File

@ -21,7 +21,7 @@
GCC_ASM_IMPORT(CEntryPoint) GCC_ASM_IMPORT(CEntryPoint)
GCC_ASM_IMPORT(ArmReadMpidr) GCC_ASM_IMPORT(ArmReadMpidr)
GCC_ASM_IMPORT(ArmIsMPCore) GCC_ASM_IMPORT(ArmIsMpCore)
GCC_ASM_EXPORT(_ModuleEntryPoint) GCC_ASM_EXPORT(_ModuleEntryPoint)
StartupAddr: .word CEntryPoint StartupAddr: .word CEntryPoint
@ -77,7 +77,7 @@ _SetupStack:
_GetStackBase: _GetStackBase:
// Compute Base of Normal stacks for CPU Cores // Compute Base of Normal stacks for CPU Cores
// Is it MpCore system // Is it MpCore system
bl ArmIsMPCore bl ArmIsMpCore
cmp r0, #0 cmp r0, #0
// Case it is not an MP Core system. Just setup the primary core // Case it is not an MP Core system. Just setup the primary core
beq _SetupUnicoreStack beq _SetupUnicoreStack

4
ArmPlatformPkg/PrePi/ModuleEntryPoint.asm
View File

@ -20,7 +20,7 @@
IMPORT CEntryPoint IMPORT CEntryPoint
IMPORT ArmReadMpidr IMPORT ArmReadMpidr
IMPORT ArmIsMPCore IMPORT ArmIsMpCore
EXPORT _ModuleEntryPoint EXPORT _ModuleEntryPoint
PRESERVE8 PRESERVE8
@ -78,7 +78,7 @@ _SetupStack
_GetStackBase _GetStackBase
// Compute Base of Normal stacks for CPU Cores // Compute Base of Normal stacks for CPU Cores
// Is it MpCore system // Is it MpCore system
bl ArmIsMPCore bl ArmIsMpCore
cmp r0, #0 cmp r0, #0
// Case it is not an MP Core system. Just setup the primary core // Case it is not an MP Core system. Just setup the primary core
beq _SetupUnicoreStack beq _SetupUnicoreStack

6
BeagleBoardPkg/Bds/Bds.inf
View File

@ -61,11 +61,5 @@
gEfiUsbIoProtocolGuid gEfiUsbIoProtocolGuid
gEfiFirmwareVolume2ProtocolGuid gEfiFirmwareVolume2ProtocolGuid
[FeaturePcd]
[FixedPcd]
gEmbeddedTokenSpaceGuid.PcdPrePiStackSize
[Depex] [Depex]
TRUE TRUE

41
BeagleBoardPkg/BeagleBoardPkg-next.dsc
View File

@ -122,7 +122,6 @@
DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
[LibraryClasses.common.SEC] [LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
@ -175,7 +174,6 @@
SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf SecurityManagementLib|MdeModulePkg/Library/DxeSecurityManagementLib/DxeSecurityManagementLib.inf
PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf PerformanceLib|MdeModulePkg/Library/DxePerformanceLib/DxePerformanceLib.inf
[LibraryClasses.common.UEFI_APPLICATION] [LibraryClasses.common.UEFI_APPLICATION]
ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf ReportStatusCodeLib|IntelFrameworkModulePkg/Library/DxeReportStatusCodeLibFramework/DxeReportStatusCodeLib.inf
UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf UefiDecompressLib|IntelFrameworkModulePkg/Library/BaseUefiTianoCustomDecompressLib/BaseUefiTianoCustomDecompressLib.inf
@ -207,18 +205,11 @@
[BuildOptions] [BuildOptions]
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8 --thumb RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8
RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
################################################################################ ################################################################################
# #
@ -309,9 +300,6 @@
gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07 gEmbeddedTokenSpaceGuid.PcdEmbeddedDefaultTextColor|0x07
gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000 gEmbeddedTokenSpaceGuid.PcdEmbeddedMemVariableStoreSize|0x10000
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase|0
gEmbeddedTokenSpaceGuid.PcdFlashFvMainSize|0
# #
# Optional feature to help prevent EFI memory map fragments # Optional feature to help prevent EFI memory map fragments
# Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob # Turned on and off via: PcdPrePiProduceMemoryTypeInformationHob
@ -347,17 +335,6 @@
# Size of the region reserved for fixed address allocations (Reserved 32MB) # Size of the region reserved for fixed address allocations (Reserved 32MB)
gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x02000000 gArmTokenSpaceGuid.PcdArmLinuxKernelMaxOffset|0x02000000
# Reserved to store the HobBase address (top of UEFI Memory Region)
# = (PcdSystemMemoryBase + PcdSystemMemorySize) - sizeof(UINT32)
gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x87FFFFFC
#gEmbeddedTokenSpaceGuid.PcdPrePiHobBase|0x80001000
gEmbeddedTokenSpaceGuid.PcdPrePiStackBase|0x87FE0000 # stack at top of memory
gEmbeddedTokenSpaceGuid.PcdPrePiStackSize|0x20000 # 128K stack
gEmbeddedTokenSpaceGuid.PcdMemoryBase|0x80000000
gEmbeddedTokenSpaceGuid.PcdMemorySize|0x10000000
gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80008000 gArmTokenSpaceGuid.PcdCpuVectorBaseAddress|0x80008000
gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000 gArmTokenSpaceGuid.PcdCpuResetAddress|0x80008000
@ -392,14 +369,14 @@
################################################################################ ################################################################################
[Components.common] [Components.common]
# #
# SEC # SEC
# #
ArmPlatformPkg/PrePi/PeiUniCore.inf ArmPlatformPkg/PrePi/PeiUniCore.inf
# #
# DXE # DXE
# #
MdeModulePkg/Core/Dxe/DxeMain.inf { MdeModulePkg/Core/Dxe/DxeMain.inf {
<LibraryClasses> <LibraryClasses>
PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf PcdLib|MdePkg/Library/BasePcdLibNull/BasePcdLibNull.inf

14
BeagleBoardPkg/BeagleBoardPkg.dsc
View File

@ -122,7 +122,6 @@
DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf DmaLib|ArmPkg/Library/ArmDmaLib/ArmDmaLib.inf
BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf BdsLib|ArmPkg/Library/BdsLib/BdsLib.inf
FdtLib|EmbeddedPkg/Library/FdtLib/FdtLib.inf
[LibraryClasses.common.SEC] [LibraryClasses.common.SEC]
ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf ArmLib|ArmPkg/Library/ArmLib/ArmV7/ArmV7LibPrePi.inf
@ -202,18 +201,11 @@
[BuildOptions] [BuildOptions]
XCODE:*_*_ARM_ARCHCC_FLAGS == -arch armv7 -march=armv7 XCODE:*_*_ARM_PLATFORM_FLAGS == -arch armv7
XCODE:*_*_ARM_ARCHASM_FLAGS == -arch armv7
XCODE:*_*_ARM_ARCHDLINK_FLAGS == -arch armv7
XCODE:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
GCC:*_*_ARM_ARCHCC_FLAGS == -march=armv7-a -mthumb GCC:*_*_ARM_PLATFORM_FLAGS == -march=armv7-a
GCC:*_*_ARM_ARCHASM_FLAGS == -march=armv7-a
GCC:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
RVCT:*_*_ARM_ARCHCC_FLAGS == --cpu Cortex-A8 --thumb RVCT:*_*_ARM_PLATFORM_FLAGS == --cpu Cortex-A8
RVCT:*_*_ARM_ARCHASM_FLAGS == --cpu Cortex-A8
RVCT:RELEASE_*_*_CC_FLAGS = -DMDEPKG_NDEBUG
################################################################################ ################################################################################
# #

1
BeagleBoardPkg/BeagleBoardPkg.fdf
View File

@ -174,7 +174,6 @@ READ_LOCK_STATUS = TRUE
INF ArmPlatformPkg/Bds/Bds.inf INF ArmPlatformPkg/Bds/Bds.inf
[FV.FVMAIN_COMPACT] [FV.FVMAIN_COMPACT]
FvAlignment = 8 FvAlignment = 8
ERASE_POLARITY = 1 ERASE_POLARITY = 1

2
BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.c
View File

@ -125,7 +125,7 @@ LibResetSystem (
switch (ResetType) { switch (ResetType) {
case EfiResetWarm: case EfiResetWarm:
//Perform warm reset of the system by jumping to the begining of the FV //Perform warm reset of the system by jumping to the begining of the FV
StartOfFv = (CALL_STUB)(UINTN)PcdGet32(PcdFlashFvMainBase); StartOfFv = (CALL_STUB)(UINTN)PcdGet32(PcdFvBaseAddress);
StartOfFv (); StartOfFv ();
break; break;
case EfiResetCold: case EfiResetCold:

2
BeagleBoardPkg/Library/ResetSystemLib/ResetSystemLib.inf
View File

@ -46,4 +46,4 @@
UefiBootServicesTableLib UefiBootServicesTableLib
[Pcd] [Pcd]
gEmbeddedTokenSpaceGuid.PcdFlashFvMainBase gArmTokenSpaceGuid.PcdFvBaseAddress

2
BeagleBoardPkg/b.bat
View File

@ -32,7 +32,7 @@ SET TARGET=DEBUG
SET BUILD_ROOT=%WORKSPACE%\Build\BeagleBoard\%TARGET%_%TARGET_TOOLS% SET BUILD_ROOT=%WORKSPACE%\Build\BeagleBoard\%TARGET%_%TARGET_TOOLS%
@REM Build the Beagle Board firmware and creat an FD (FLASH Device) Image. @REM Build the Beagle Board firmware and creat an FD (FLASH Device) Image.
CALL build -p BeagleBoardPkg\BeagleBoardPkg.dsc -a ARM -t RVCT31 -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8 CALL build -p BeagleBoardPkg\BeagleBoardPkg.dsc -a ARM -t %TARGET_TOOLS% -b %TARGET% %1 %2 %3 %4 %5 %6 %7 %8
@if ERRORLEVEL 1 goto Exit @if ERRORLEVEL 1 goto Exit
@if /I "%1"=="CLEAN" goto Clean @if /I "%1"=="CLEAN" goto Clean

2
BeagleBoardPkg/build-next.sh
View File

@ -137,7 +137,7 @@ rm -f $FLASH_BOOT
# point looks so strange. # point looks so strange.
# OMAP 3430 TRM section 26.4.8 has Image header information. (missing in OMAP 3530 TRM) # OMAP 3430 TRM section 26.4.8 has Image header information. (missing in OMAP 3530 TRM)
# #
$GENERATE_IMAGE -D $WORKSPACE/BeagleBoardPkg/ConfigurationHeader.dat -E 0x80008208 -I $BUILD_ROOT/FV/BEAGLEBOARD_EFI.fd -O $FLASH_BOOT $GENERATE_IMAGE -D $WORKSPACE/BeagleBoardPkg/ConfigurationHeader.dat -E 0x80008000 -I $BUILD_ROOT/FV/BEAGLEBOARD_EFI.fd -O $FLASH_BOOT
echo Creating debugger scripts echo Creating debugger scripts
process_debug_scripts $WORKSPACE/BeagleBoardPkg/Debugger_scripts process_debug_scripts $WORKSPACE/BeagleBoardPkg/Debugger_scripts