mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg: Add CPUID definitions for AMD.
Cc: Jordan Justen <jordan.l.justen@intel.com> Cc: Jeff Fan <jeff.fan@intel.com> Cc: Liming Gao <liming.gao@intel.com> Cc: Brijesh Singh <brijesh.singh@amd.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Leo Duran <leo.duran@amd.com> Reviewed-by: Jeff Fan <jeff.fan@intel.com>
This commit is contained in:
Leo Duran
Jeff Fan
parent
b15cbd9c2d
commit
890d2bd287
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@ -7,6 +7,7 @@
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not provided for that register.
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Copyright (c) 2017, Advanced Micro Devices. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available
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under the terms and conditions of the BSD License which accompanies this
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distribution. The full text of the license may be found at
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@ -24,8 +25,587 @@
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#define __AMD_CPUID_H__
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/**
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CPUID Signature Information
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Memory Encryption Information
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@param EAX CPUID_SIGNATURE (0x00)
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@retval EAX Returns the highest value the CPUID instruction recognizes for
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returning basic processor information. The value is returned is
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processor specific.
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@retval EBX First 4 characters of a vendor identification string.
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@retval ECX Last 4 characters of a vendor identification string.
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@retval EDX Middle 4 characters of a vendor identification string.
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**/
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///
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/// @{ CPUID signature values returned by AMD processors
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///
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#define CPUID_SIGNATURE_AUTHENTIC_AMD_EBX SIGNATURE_32 ('A', 'u', 't', 'h')
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#define CPUID_SIGNATURE_AUTHENTIC_AMD_EDX SIGNATURE_32 ('e', 'n', 't', 'i')
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#define CPUID_SIGNATURE_AUTHENTIC_AMD_ECX SIGNATURE_32 ('c', 'A', 'M', 'D')
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///
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/// @}
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///
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/**
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CPUID Extended Processor Signature and Features
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@param EAX CPUID_EXTENDED_CPU_SIG (0x80000001)
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@retval EAX Extended Family, Model, Stepping Identifiers
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described by the type CPUID_AMD_EXTENDED_CPU_SIG_EAX.
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@retval EBX Brand Identifier
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described by the type CPUID_AMD_EXTENDED_CPU_SIG_EBX.
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@retval ECX Extended Feature Identifiers
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described by the type CPUID_AMD_EXTENDED_CPU_SIG_ECX.
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@retval EDX Extended Feature Identifiers
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described by the type CPUID_AMD_EXTENDED_CPU_SIG_EDX.
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**/
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/**
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CPUID Extended Processor Signature and Features EAX for CPUID leaf
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#CPUID_EXTENDED_CPU_SIG.
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 3:0] Stepping.
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///
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UINT32 Stepping:4;
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///
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/// [Bits 7:4] Base Model.
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///
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UINT32 BaseModel:4;
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///
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/// [Bits 11:8] Base Family.
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///
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UINT32 BaseFamily:4;
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///
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/// [Bit 15:12] Reserved.
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///
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UINT32 Reserved1:4;
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///
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/// [Bits 19:16] Extended Model.
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///
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UINT32 ExtModel:4;
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///
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/// [Bits 27:20] Extended Family.
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///
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UINT32 ExtFamily:8;
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///
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/// [Bit 31:28] Reserved.
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///
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UINT32 Reserved2:4;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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} CPUID_AMD_EXTENDED_CPU_SIG_EAX;
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/**
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CPUID Extended Processor Signature and Features EBX for CPUID leaf
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#CPUID_EXTENDED_CPU_SIG.
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 27:0] Reserved.
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///
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UINT32 Reserved:28;
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///
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/// [Bit 31:28] Package Type.
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///
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UINT32 PkgType:4;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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} CPUID_AMD_EXTENDED_CPU_SIG_EBX;
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/**
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CPUID Extended Processor Signature and Features ECX for CPUID leaf
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#CPUID_EXTENDED_CPU_SIG.
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] LAHF/SAHF available in 64-bit mode.
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///
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UINT32 LAHF_SAHF:1;
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///
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/// [Bit 1] Core multi-processing legacy mode.
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///
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UINT32 CmpLegacy:1;
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///
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/// [Bit 2] Secure Virtual Mode feature.
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///
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UINT32 SVM:1;
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///
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/// [Bit 3] Extended APIC register space.
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///
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UINT32 ExtApicSpace:1;
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///
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/// [Bit 4] LOCK MOV CR0 means MOV CR8.
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///
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UINT32 AltMovCr8:1;
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///
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/// [Bit 5] LZCNT instruction support.
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///
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UINT32 LZCNT:1;
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///
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/// [Bit 6] SSE4A instruction support.
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///
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UINT32 SSE4A:1;
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///
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/// [Bit 7] Misaligned SSE Mode.
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///
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UINT32 MisAlignSse:1;
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///
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/// [Bit 8] ThreeDNow Prefetch instructions.
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///
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UINT32 PREFETCHW:1;
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///
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/// [Bit 9] OS Visible Work-around support.
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///
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UINT32 OSVW:1;
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///
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/// [Bit 10] Instruction Based Sampling.
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///
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UINT32 IBS:1;
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///
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/// [Bit 11] Extended Operation Support.
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///
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UINT32 XOP:1;
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///
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/// [Bit 12] SKINIT and STGI support.
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///
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UINT32 SKINIT:1;
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///
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/// [Bit 13] Watchdog Timer support.
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///
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UINT32 WDT:1;
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///
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/// [Bit 14] Reserved.
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///
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UINT32 Reserved1:1;
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///
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/// [Bit 15] Lightweight Profiling support.
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///
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UINT32 LWP:1;
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///
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/// [Bit 16] 4-Operand FMA instruction support.
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///
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UINT32 FMA4:1;
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///
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/// [Bit 17] Translation Cache Extension.
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///
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UINT32 TCE:1;
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///
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/// [Bit 21:18] Reserved.
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///
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UINT32 Reserved2:4;
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///
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/// [Bit 22] Topology Extensions support.
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///
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UINT32 TopologyExtensions:1;
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///
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/// [Bit 23] Core Performance Counter Extensions.
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///
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UINT32 PerfCtrExtCore:1;
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///
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/// [Bit 25:24] Reserved.
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///
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UINT32 Reserved3:2;
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///
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/// [Bit 26] Data Breakpoint Extension.
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///
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UINT32 DataBreakpointExtension:1;
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///
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/// [Bit 27] Performance Time-Stamp Counter.
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///
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UINT32 PerfTsc:1;
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///
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/// [Bit 28] L3 Performance Counter Extensions.
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///
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UINT32 PerfCtrExtL3:1;
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///
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/// [Bit 29] MWAITX and MONITORX capability.
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///
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UINT32 MwaitExtended:1;
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///
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/// [Bit 31:30] Reserved.
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///
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UINT32 Reserved4:2;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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} CPUID_AMD_EXTENDED_CPU_SIG_ECX;
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/**
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CPUID Extended Processor Signature and Features EDX for CPUID leaf
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#CPUID_EXTENDED_CPU_SIG.
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bit 0] x87 floating point unit on-chip.
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///
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UINT32 FPU:1;
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///
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/// [Bit 1] Virtual-mode enhancements.
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///
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UINT32 VME:1;
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///
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/// [Bit 2] Debugging extensions, IO breakpoints, CR4.DE.
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///
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UINT32 DE:1;
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///
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/// [Bit 3] Page-size extensions (4 MB pages).
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///
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UINT32 PSE:1;
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///
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/// [Bit 4] Time stamp counter, RDTSC/RDTSCP instructions, CR4.TSD.
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///
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UINT32 TSC:1;
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///
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/// [Bit 5] MSRs, with RDMSR and WRMSR instructions.
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///
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UINT32 MSR:1;
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///
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/// [Bit 6] Physical-address extensions (PAE).
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///
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UINT32 PAE:1;
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///
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/// [Bit 7] Machine check exception, CR4.MCE.
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///
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UINT32 MCE:1;
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///
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/// [Bit 8] CMPXCHG8B instruction.
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///
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UINT32 CMPXCHG8B:1;
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///
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/// [Bit 9] APIC exists and is enabled.
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///
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UINT32 APIC:1;
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///
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/// [Bit 10] Reserved.
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///
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UINT32 Reserved1:1;
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///
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/// [Bit 11] SYSCALL and SYSRET instructions.
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///
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UINT32 SYSCALL_SYSRET:1;
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///
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/// [Bit 12] Memory-type range registers.
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///
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UINT32 MTRR:1;
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///
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/// [Bit 13] Page global extension, CR4.PGE.
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///
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UINT32 PGE:1;
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///
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/// [Bit 14] Machine check architecture, MCG_CAP.
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///
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UINT32 MCA:1;
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///
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/// [Bit 15] Conditional move instructions, CMOV, FCOMI, FCMOV.
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///
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UINT32 CMOV:1;
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///
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/// [Bit 16] Page attribute table.
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///
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UINT32 PAT:1;
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///
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/// [Bit 17] Page-size extensions.
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///
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UINT32 PSE36 : 1;
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///
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/// [Bit 19:18] Reserved.
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///
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UINT32 Reserved2:2;
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///
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/// [Bit 20] No-execute page protection.
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///
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UINT32 NX:1;
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///
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/// [Bit 21] Reserved.
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///
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UINT32 Reserved3:1;
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///
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/// [Bit 22] AMD Extensions to MMX instructions.
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///
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UINT32 MmxExt:1;
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///
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/// [Bit 23] MMX instructions.
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///
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UINT32 MMX:1;
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///
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/// [Bit 24] FXSAVE and FXRSTOR instructions.
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///
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UINT32 FFSR:1;
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///
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/// [Bit 25] FXSAVE and FXRSTOR instruction optimizations.
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///
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UINT32 FFXSR:1;
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///
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/// [Bit 26] 1-GByte large page support.
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///
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UINT32 Page1GB:1;
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///
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/// [Bit 27] RDTSCP intructions.
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///
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UINT32 RDTSCP:1;
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///
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/// [Bit 28] Reserved.
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///
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UINT32 Reserved4:1;
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///
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/// [Bit 29] Long Mode.
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///
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UINT32 LM:1;
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///
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/// [Bit 30] 3DNow! instructions.
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///
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UINT32 ThreeDNow:1;
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///
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/// [Bit 31] AMD Extensions to 3DNow! instructions.
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///
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UINT32 ThreeDNowExt:1;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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} CPUID_AMD_EXTENDED_CPU_SIG_EDX;
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/**
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CPUID Linear Physical Address Size
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@param EAX CPUID_VIR_PHY_ADDRESS_SIZE (0x80000008)
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@retval EAX Linear/Physical Address Size described by the type
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CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX.
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@retval EBX Linear/Physical Address Size described by the type
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CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX.
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@retval ECX Linear/Physical Address Size described by the type
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CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX.
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@retval EDX Reserved.
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**/
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/**
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CPUID Linear Physical Address Size EAX for CPUID leaf
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#CPUID_VIR_PHY_ADDRESS_SIZE.
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 7:0] Maximum physical byte address size in bits.
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///
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UINT32 PhysicalAddressBits:8;
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///
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/// [Bits 15:8] Maximum linear byte address size in bits.
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///
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UINT32 LinearAddressBits:8;
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///
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/// [Bits 23:16] Maximum guest physical byte address size in bits.
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///
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UINT32 GuestPhysAddrSize:8;
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///
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/// [Bit 31:24] Reserved.
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///
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UINT32 Reserved:8;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EAX;
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/**
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CPUID Linear Physical Address Size EBX for CPUID leaf
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#CPUID_VIR_PHY_ADDRESS_SIZE.
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 0] Clear Zero Instruction.
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///
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UINT32 CLZERO:1;
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///
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/// [Bits 1] Instructions retired count support.
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///
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UINT32 IRPerf:1;
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///
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/// [Bits 2] Restore error pointers for XSave instructions.
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///
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UINT32 XSaveErPtr:1;
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///
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/// [Bit 31:3] Reserved.
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///
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UINT32 Reserved:29;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_EBX;
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/**
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CPUID Linear Physical Address Size ECX for CPUID leaf
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#CPUID_VIR_PHY_ADDRESS_SIZE.
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**/
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typedef union {
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///
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/// Individual bit fields
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///
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struct {
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///
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/// [Bits 7:0] Number of threads - 1.
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///
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UINT32 NC:8;
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///
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/// [Bit 11:8] Reserved.
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///
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UINT32 Reserved1:4;
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///
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/// [Bits 15:12] APIC ID size.
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///
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UINT32 ApicIdCoreIdSize:4;
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///
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/// [Bits 17:16] Performance time-stamp counter size.
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///
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UINT32 PerfTscSize:2;
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///
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/// [Bit 31:18] Reserved.
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///
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UINT32 Reserved2:14;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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} CPUID_AMD_VIR_PHY_ADDRESS_SIZE_ECX;
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/**
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CPUID AMD Processor Topology
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@param EAX CPUID_AMD_PROCESSOR_TOPOLOGY (0x8000001E)
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@retval EAX Extended APIC ID described by the type
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CPUID_AMD_PROCESSOR_TOPOLOGY_EAX.
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@retval EBX Core Indentifiers described by the type
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CPUID_AMD_PROCESSOR_TOPOLOGY_EBX.
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@retval ECX Node Indentifiers described by the type
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CPUID_AMD_PROCESSOR_TOPOLOGY_ECX.
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@retval EDX Reserved.
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**/
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#define CPUID_AMD_PROCESSOR_TOPOLOGY 0x8000001E
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/**
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CPUID AMD Processor Topology EAX for CPUID leaf
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#CPUID_AMD_PROCESSOR_TOPOLOGY.
|
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**/
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typedef union {
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///
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/// Individual bit fields
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///
|
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struct {
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///
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/// [Bit 31:0] Extended APIC Id.
|
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///
|
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UINT32 ExtendedApicId;
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} Bits;
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///
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/// All bit fields as a 32-bit value
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///
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UINT32 Uint32;
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} CPUID_AMD_PROCESSOR_TOPOLOGY_EAX;
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/**
|
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CPUID AMD Processor Topology EBX for CPUID leaf
|
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#CPUID_AMD_PROCESSOR_TOPOLOGY.
|
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**/
|
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typedef union {
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///
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/// Individual bit fields
|
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///
|
||||
struct {
|
||||
///
|
||||
/// [Bits 7:0] Core Id.
|
||||
///
|
||||
UINT32 CoreId:8;
|
||||
///
|
||||
/// [Bits 15:8] Threads per core.
|
||||
///
|
||||
UINT32 ThreadsPerCore:8;
|
||||
///
|
||||
/// [Bit 31:16] Reserved.
|
||||
///
|
||||
UINT32 Reserved:16;
|
||||
} Bits;
|
||||
///
|
||||
/// All bit fields as a 32-bit value
|
||||
///
|
||||
UINT32 Uint32;
|
||||
} CPUID_AMD_PROCESSOR_TOPOLOGY_EBX;
|
||||
|
||||
/**
|
||||
CPUID AMD Processor Topology ECX for CPUID leaf
|
||||
#CPUID_AMD_PROCESSOR_TOPOLOGY.
|
||||
**/
|
||||
typedef union {
|
||||
///
|
||||
/// Individual bit fields
|
||||
///
|
||||
struct {
|
||||
///
|
||||
/// [Bits 7:0] Node Id.
|
||||
///
|
||||
UINT32 NodeId:8;
|
||||
///
|
||||
/// [Bits 10:8] Nodes per processor.
|
||||
///
|
||||
UINT32 NodesPerProcessor:3;
|
||||
///
|
||||
/// [Bit 31:11] Reserved.
|
||||
///
|
||||
UINT32 Reserved:21;
|
||||
} Bits;
|
||||
///
|
||||
/// All bit fields as a 32-bit value
|
||||
///
|
||||
UINT32 Uint32;
|
||||
} CPUID_AMD_PROCESSOR_TOPOLOGY_ECX;
|
||||
|
||||
|
||||
/**
|
||||
CPUID Memory Encryption Information
|
||||
|
||||
@param EAX CPUID_MEMORY_ENCRYPTION_INFO (0x8000001F)
|
||||
|
||||
|
|
@ -33,8 +613,8 @@
|
|||
@retval EBX If memory encryption feature is present then return
|
||||
the page table bit number used to enable memory encryption support
|
||||
and reducing of physical address space in bits.
|
||||
@retval ECX Returns number of encrypted guest supported simultaneosuly.
|
||||
@retval EDX Returns minimum SEV enabled and SEV disbled ASID..
|
||||
@retval ECX Returns number of encrypted guest supported simultaneously.
|
||||
@retval EDX Returns minimum SEV enabled and SEV disabled ASID.
|
||||
|
||||
<b>Example usage</b>
|
||||
@code
|
||||
|
|
@ -79,7 +659,7 @@ typedef union {
|
|||
UINT32 SevEsBit:1;
|
||||
|
||||
///
|
||||
/// [Bit 4:31] Reserved
|
||||
/// [Bit 31:4] Reserved
|
||||
///
|
||||
UINT32 ReservedBits:28;
|
||||
} Bits;
|
||||
|
|
@ -99,17 +679,18 @@ typedef union {
|
|||
///
|
||||
struct {
|
||||
///
|
||||
/// [Bit 0:5] Page table bit number used to enable memory encryption
|
||||
/// [Bit 5:0] Page table bit number used to enable memory encryption
|
||||
///
|
||||
UINT32 PtePosBits:6;
|
||||
|
||||
///
|
||||
/// [Bit 6:11] Reduction of system physical address space bits when memory encryption is enabled
|
||||
/// [Bit 11:6] Reduction of system physical address space bits when
|
||||
/// memory encryption is enabled
|
||||
///
|
||||
UINT32 ReducedPhysBits:5;
|
||||
|
||||
///
|
||||
/// [Bit 12:31] Reserved
|
||||
/// [Bit 31:12] Reserved
|
||||
///
|
||||
UINT32 ReservedBits:21;
|
||||
} Bits;
|
||||
|
|
@ -129,7 +710,7 @@ typedef union {
|
|||
///
|
||||
struct {
|
||||
///
|
||||
/// [Bit 0:31] Number of encrypted guest supported simultaneously
|
||||
/// [Bit 31:0] Number of encrypted guest supported simultaneously
|
||||
///
|
||||
UINT32 NumGuests;
|
||||
} Bits;
|
||||
|
|
@ -149,7 +730,7 @@ typedef union {
|
|||
///
|
||||
struct {
|
||||
///
|
||||
/// [Bit 0:31] Minimum SEV enabled, SEV-ES disabled ASID
|
||||
/// [Bit 31:0] Minimum SEV enabled, SEV-ES disabled ASID
|
||||
///
|
||||
UINT32 MinAsid;
|
||||
} Bits;
|
||||
|
|
|
|||
Loading…
Reference in New Issue