mirror of https://github.com/acidanthera/audk.git
Vlv2TbltDevicePkg/PlatformInitPei: Workaround unaligned SMRAM size
https://bugzilla.tianocore.org/show_bug.cgi?id=260 The PiSmmCPuDxeSmm module requires the SMRR base address and length to be aligned. The memory initialization for Vlv2TbltDevicePkg produces an SMRAM base address that is on a 16MB boundary and an SMRAM length of 12MB. The SMRAM length is rounded up to 16MB. This is a workaround until the binary module that produces the gEfiSmmPeiSmramMemoryReserveGuid HOB is updated Cc: Jiewen Yao <jiewen.yao@intel.com> Cc: David Wei <david.wei@intel.com> Cc: Mang Guo <mang.guo@intel.com> Contributed-under: TianoCore Contribution Agreement 1.0 Signed-off-by: Michael Kinney <michael.d.kinney@intel.com> Reviewed-by: Jiewen Yao <jiewen.yao@intel.com>
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@ -1,6 +1,6 @@
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/** @file
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/** @file
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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the terms and conditions of the BSD License that accompanies this distribution.
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@ -820,6 +820,19 @@ PlatformEarlyInitEntry (
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EFI_PLATFORM_INFO_HOB *PlatformInfo;
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EFI_PLATFORM_INFO_HOB *PlatformInfo;
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EFI_PEI_HOB_POINTERS Hob;
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EFI_PEI_HOB_POINTERS Hob;
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EFI_PLATFORM_CPU_INFO PlatformCpuInfo;
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EFI_PLATFORM_CPU_INFO PlatformCpuInfo;
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EFI_SMRAM_HOB_DESCRIPTOR_BLOCK *DescriptorBlock;
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UINT64 Size;
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//
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// Make sure last SMRAM region is aligned
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//
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Hob.Raw = GetFirstGuidHob (&gEfiSmmPeiSmramMemoryReserveGuid);
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if (Hob.Raw != NULL) {
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DescriptorBlock = GET_GUID_HOB_DATA (Hob.Raw);
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Size = DescriptorBlock->Descriptor[DescriptorBlock->NumberOfSmmReservedRegions - 1].PhysicalSize;
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Size = LShiftU64 (1, HighBitSet64 (Size - 1) + 1);
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DescriptorBlock->Descriptor[DescriptorBlock->NumberOfSmmReservedRegions - 1].PhysicalSize = Size;
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}
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//
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//
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// Initialize SmbusPolicy PPI
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// Initialize SmbusPolicy PPI
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@ -1,6 +1,6 @@
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/*++
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/*++
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Copyright (c) 2004 - 2014, Intel Corporation. All rights reserved.<BR>
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Copyright (c) 2004 - 2016, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License that accompanies this distribution.
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the terms and conditions of the BSD License that accompanies this distribution.
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@ -83,6 +83,7 @@ Abstract:
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#include <Ppi/MasterBootMode.h>
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#include <Ppi/MasterBootMode.h>
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#include <Guid/PlatformCpuInfo.h>
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#include <Guid/PlatformCpuInfo.h>
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#include <Guid/OsSelection.h>
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#include <Guid/OsSelection.h>
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#include <Guid/SmramMemoryReserve.h>
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#define SMC_LAN_ON 0x46
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#define SMC_LAN_ON 0x46
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#define SMC_LAN_OFF 0x47
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#define SMC_LAN_OFF 0x47
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#
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#
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#
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#
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# Copyright (c) 1999 - 2014, Intel Corporation. All rights reserved
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# Copyright (c) 1999 - 2016, Intel Corporation. All rights reserved
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#
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#
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# This program and the accompanying materials are licensed and made available under
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# This program and the accompanying materials are licensed and made available under
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# the terms and conditions of the BSD License that accompanies this distribution.
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# the terms and conditions of the BSD License that accompanies this distribution.
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@ -102,6 +102,7 @@ ENTRY_POINT = PlatformEarlyInitEntry
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gEfiNormalSetupGuid
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gEfiNormalSetupGuid
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gEfiMemoryTypeInformationGuid
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gEfiMemoryTypeInformationGuid
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gOsSelectionVariableGuid
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gOsSelectionVariableGuid
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gEfiSmmPeiSmramMemoryReserveGuid
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[Pcd.common]
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[Pcd.common]
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gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
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gPlatformModuleTokenSpaceGuid.PcdFlashFvMainBase
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