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CorebootModulePkg/PciHostBridgeLib: Fix PCI 64bit memory BAR size issue 

The current PCI 64bit memory BAR size calculation in PciHostBridgeLib
assumes all 32 bits in the upper BAR are fully writable. However,
platform might only support partial address programming, such as 40bit
PCI BAR address. In this case the complement cannot be used for size
calculation.  Instead, the lowest non-zero bit should be used for BAR
size calculation.

Cc: Prince Agyeman <prince.agyeman@intel.com>
Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Maurice Ma <maurice.ma@intel.com>
Reviewed-by: Prince Agyeman <prince.agyeman@intel.com>
This commit is contained in:
Maurice Ma 2016-05-26 15:13:23 -07:00
parent ee70e58bd2
commit 8a3a97814e
1 changed files with 5 additions and 1 deletions
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6
CorebootPayloadPkg/Library/PciHostBridgeLib/PciHostBridgeSupport.c
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@ -193,6 +193,7 @@ PcatPciRootBridgeParseBars (
UINT32 UpperValue;
UINT64 Mask;
UINTN Offset;
UINTN LowBit;
UINT64 Base;
UINT64 Length;
UINT64 Limit;
@ -262,7 +263,10 @@ PcatPciRootBridgeParseBars (
Base = Base | LShiftU64 ((UINT64) OriginalUpperValue, 32);
Length = Length | LShiftU64 ((UINT64) UpperValue, 32);
Length = (~Length) + 1;
if (Length != 0) {
LowBit = LowBitSet64 (Length);
Length = LShiftU64 (1ULL, LowBit);
}
if ((Value & BIT3) == BIT3) {
MemAperture = PMemAbove4G;