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ArmPkg/ArmLib: Fixed AArch64 MMU code when a region overlaps 2 level-3 page tables 

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Olivier Martin <olivier.martin@arm.com>



git-svn-id: https://svn.code.sf.net/p/edk2/code/trunk/edk2@15483 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
Olivier Martin 2014-04-24 10:37:48 +00:00 committed by oliviermartin
parent 50c455da00
commit 8bb7f03ade
1 changed files with 10 additions and 3 deletions
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13
ArmPkg/Library/ArmLib/AArch64/AArch64Mmu.c
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@ -397,8 +397,11 @@ GetBlockEntryListFromAddress (
BlockEntry = TranslationTable;
}
} else {
// Case of Invalid Entry and we are at a page level above of the one targetted.
if (IndexLevel != PageLevel) {
//
// Case when we have an Invalid Entry and we are at a page level above of the one targetted.
//
// Create a new translation table
TranslationTable = (UINT64*)AllocatePages (EFI_SIZE_TO_PAGES((TT_ENTRY_COUNT * sizeof(UINT64)) + TT_ALIGNMENT_DESCRIPTION_TABLE));
if (TranslationTable == NULL) {
@ -412,6 +415,11 @@ GetBlockEntryListFromAddress (
*BlockEntry = ((UINTN)TranslationTable & TT_ADDRESS_MASK_DESCRIPTION_TABLE) | TT_TYPE_TABLE_ENTRY;
// Update the last block entry with the newly created translation table
*LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, TT_ENTRY_COUNT);
} else {
//
// Case when the new region is part of an existing page table
//
*LastBlockEntry = TT_LAST_BLOCK_ADDRESS(TranslationTable, TT_ENTRY_COUNT);
}
}
}
@ -531,8 +539,7 @@ ArmConfigureMmu (
UINT64 TCR;
RETURN_STATUS Status;
if(MemoryTable == NULL)
{
if(MemoryTable == NULL) {
ASSERT (MemoryTable != NULL);
return RETURN_INVALID_PARAMETER;
}