mirror of
https://github.com/acidanthera/audk.git
synced 2025-07-24 06:04:52 +02:00
ArmPkg: Adjust variable type and cast for RegShift & RegOffset
According to the GIC architecture version 3 and 4 specification, the maximum number of INTID bits supported in the CPU interface is 24. Considering this the RegShift variable is not required to be more than 8 bits. Therefore, make the RegShift variable type to UINT8. Also add necessary typecasts when calculating the RegOffset and RegShift values. Signed-off-by: Sami Mujawar <sami.mujawar@arm.com>
This commit is contained in:
parent
8da2b97392
commit
8bcddbcce2
@ -228,13 +228,13 @@ ArmGicSetInterruptPriority (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
UINT32 RegOffset;
|
UINT32 RegOffset;
|
||||||
UINTN RegShift;
|
UINT8 RegShift;
|
||||||
ARM_GIC_ARCH_REVISION Revision;
|
ARM_GIC_ARCH_REVISION Revision;
|
||||||
UINTN GicCpuRedistributorBase;
|
UINTN GicCpuRedistributorBase;
|
||||||
|
|
||||||
// Calculate register offset and bit position
|
// Calculate register offset and bit position
|
||||||
RegOffset = Source / 4;
|
RegOffset = (UINT32)(Source / 4);
|
||||||
RegShift = (Source % 4) * 8;
|
RegShift = (UINT8)((Source % 4) * 8);
|
||||||
|
|
||||||
Revision = ArmGicGetSupportedArchRevision ();
|
Revision = ArmGicGetSupportedArchRevision ();
|
||||||
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
|
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
|
||||||
@ -272,13 +272,13 @@ ArmGicEnableInterrupt (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
UINT32 RegOffset;
|
UINT32 RegOffset;
|
||||||
UINTN RegShift;
|
UINT8 RegShift;
|
||||||
ARM_GIC_ARCH_REVISION Revision;
|
ARM_GIC_ARCH_REVISION Revision;
|
||||||
UINTN GicCpuRedistributorBase;
|
UINTN GicCpuRedistributorBase;
|
||||||
|
|
||||||
// Calculate enable register offset and bit position
|
// Calculate enable register offset and bit position
|
||||||
RegOffset = Source / 32;
|
RegOffset = (UINT32)(Source / 32);
|
||||||
RegShift = Source % 32;
|
RegShift = (UINT8)(Source % 32);
|
||||||
|
|
||||||
Revision = ArmGicGetSupportedArchRevision ();
|
Revision = ArmGicGetSupportedArchRevision ();
|
||||||
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
|
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
|
||||||
@ -317,13 +317,13 @@ ArmGicDisableInterrupt (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
UINT32 RegOffset;
|
UINT32 RegOffset;
|
||||||
UINTN RegShift;
|
UINT8 RegShift;
|
||||||
ARM_GIC_ARCH_REVISION Revision;
|
ARM_GIC_ARCH_REVISION Revision;
|
||||||
UINTN GicCpuRedistributorBase;
|
UINTN GicCpuRedistributorBase;
|
||||||
|
|
||||||
// Calculate enable register offset and bit position
|
// Calculate enable register offset and bit position
|
||||||
RegOffset = Source / 32;
|
RegOffset = (UINT32)(Source / 32);
|
||||||
RegShift = Source % 32;
|
RegShift = (UINT8)(Source % 32);
|
||||||
|
|
||||||
Revision = ArmGicGetSupportedArchRevision ();
|
Revision = ArmGicGetSupportedArchRevision ();
|
||||||
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
|
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
|
||||||
@ -361,14 +361,14 @@ ArmGicIsInterruptEnabled (
|
|||||||
)
|
)
|
||||||
{
|
{
|
||||||
UINT32 RegOffset;
|
UINT32 RegOffset;
|
||||||
UINTN RegShift;
|
UINT8 RegShift;
|
||||||
ARM_GIC_ARCH_REVISION Revision;
|
ARM_GIC_ARCH_REVISION Revision;
|
||||||
UINTN GicCpuRedistributorBase;
|
UINTN GicCpuRedistributorBase;
|
||||||
UINT32 Interrupts;
|
UINT32 Interrupts;
|
||||||
|
|
||||||
// Calculate enable register offset and bit position
|
// Calculate enable register offset and bit position
|
||||||
RegOffset = Source / 32;
|
RegOffset = (UINT32)(Source / 32);
|
||||||
RegShift = Source % 32;
|
RegShift = (UINT8)(Source % 32);
|
||||||
|
|
||||||
Revision = ArmGicGetSupportedArchRevision ();
|
Revision = ArmGicGetSupportedArchRevision ();
|
||||||
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
|
if ((Revision == ARM_GIC_ARCH_REVISION_2) ||
|
||||||
|
@ -393,7 +393,7 @@ GicV2DxeInitialize (
|
|||||||
EFI_STATUS Status;
|
EFI_STATUS Status;
|
||||||
UINTN Index;
|
UINTN Index;
|
||||||
UINT32 RegOffset;
|
UINT32 RegOffset;
|
||||||
UINTN RegShift;
|
UINT8 RegShift;
|
||||||
UINT32 CpuTarget;
|
UINT32 CpuTarget;
|
||||||
|
|
||||||
// Make sure the Interrupt Controller Protocol is not already installed in
|
// Make sure the Interrupt Controller Protocol is not already installed in
|
||||||
@ -411,8 +411,8 @@ GicV2DxeInitialize (
|
|||||||
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
|
GicV2DisableInterruptSource (&gHardwareInterruptV2Protocol, Index);
|
||||||
|
|
||||||
// Set Priority
|
// Set Priority
|
||||||
RegOffset = Index / 4;
|
RegOffset = (UINT32)(Index / 4);
|
||||||
RegShift = (Index % 4) * 8;
|
RegShift = (UINT8)((Index % 4) * 8);
|
||||||
MmioAndThenOr32 (
|
MmioAndThenOr32 (
|
||||||
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
|
mGicDistributorBase + ARM_GIC_ICDIPR + (4 * RegOffset),
|
||||||
~(0xff << RegShift),
|
~(0xff << RegShift),
|
||||||
|
Loading…
x
Reference in New Issue
Block a user