mirror of https://github.com/acidanthera/audk.git
Updated MMC/SD Card driver to support hot add and remove of the media (SD Cards) and enable write protect of SD Cards. Had to update pads for WP bit as it was not being programmed as a GPIO. I also changed some of the PAD #defins as there were only really 3 states, so OR things in the table in the .c file did not make a lot of sense.
git-svn-id: https://edk2.svn.sourceforge.net/svnroot/edk2/trunk/edk2@10450 6f19259b-4bc3-4df7-8a09-765794883524
This commit is contained in:
parent
0a0951ea84
commit
8c6151f2ba
|
@ -21,244 +21,244 @@
|
|||
|
||||
PAD_CONFIGURATION PadConfigurationTable[NUM_PINS] = {
|
||||
//Pin, MuxMode, PullConfig, InputEnable
|
||||
{ SDRC_D0, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D1, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D2, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D3, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D4, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D5, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D6, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D7, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D8, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D9, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D10, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D11, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D12, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D13, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D14, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D15, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D16, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D17, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D18, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D19, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D20, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D21, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D22, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D23, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D24, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D25, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D26, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D27, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D28, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D29, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D30, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_D31, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_CLK, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_DQS0, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_CKE0, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ SDRC_CKE1, MUXMODE7, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_DQS1, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_DQS2, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ SDRC_DQS3, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_A1, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_A2, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_A3, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_A4, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_A5, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_A6, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_A7, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_A8, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_A9, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_A10, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_D0, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D1, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D2, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D3, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D4, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D5, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D6, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D7, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D8, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D9, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D10, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D11, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D12, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D13, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D14, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_D15, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_NCS0, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_NCS1, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
|
||||
{ GPMC_NCS2, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
|
||||
{ GPMC_NCS3, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
|
||||
{ GPMC_NCS4, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
|
||||
{ GPMC_NCS5, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_NCS6, MUXMODE1, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_NCS7, MUXMODE1, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ GPMC_CLK, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_NADV_ALE, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_NOE, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_NWE, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_NBE0_CLE, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ GPMC_NBE1, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_NWP, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ GPMC_WAIT0, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ GPMC_WAIT1, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ GPMC_WAIT2, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ GPMC_WAIT3, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ DSS_PCLK, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_HSYNC, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_PSYNC, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_ACBIAS, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA0, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA1, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA2, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA3, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA4, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA5, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA6, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA7, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA8, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA9, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA10, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA11, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA12, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA13, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA14, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA15, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA16, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA17, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA18, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA19, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA20, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA21, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA22, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ DSS_DATA23, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ CAM_HS, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ CAM_VS, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ CAM_XCLKA, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ CAM_PCLK, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ CAM_FLD, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ CAM_D0, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D1, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D2, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D3, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D4, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D5, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D6, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D7, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D8, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D9, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D10, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_D11, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_XCLKB, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ CAM_WEN, MUXMODE4, PULLTYPENOSELECT, INPUT },
|
||||
{ CAM_STROBE, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ CSI2_DX0, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CSI2_DY0, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CSI2_DX1, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ CSI2_DY1, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ MCBSP2_FSX, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ MCBSP2_CLKX, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ MCBSP2_DR, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ MCBSP2_DX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ MMC1_CLK, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
|
||||
{ MMC1_CMD, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC1_DAT0, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC1_DAT1, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC1_DAT2, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC1_DAT3, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC1_DAT4, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC1_DAT5, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC1_DAT6, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC1_DAT7, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_CLK, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_CMD, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_DAT0, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_DAT1, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_DAT2, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_DAT3, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_DAT4, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_DAT5, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_DAT6, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MMC2_DAT7, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MCBSP3_DX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ MCBSP3_DR, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ MCBSP3_CLKX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ MCBSP3_FSX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ UART2_CTS, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ UART2_RTS, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ UART2_TX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ UART2_RX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ UART1_TX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ UART1_RTS, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ UART1_CTS, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ UART1_RX, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ MCBSP4_CLKX, MUXMODE1, PULLTYPENOSELECT, INPUT },
|
||||
{ MCBSP4_DR, MUXMODE1, PULLTYPENOSELECT, INPUT },
|
||||
{ MCBSP4_DX, MUXMODE1, PULLTYPENOSELECT, INPUT },
|
||||
{ MCBSP4_FSX, MUXMODE1, PULLTYPENOSELECT, INPUT },
|
||||
{ MCBSP1_CLKR, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ MCBSP1_FSR, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
|
||||
{ MCBSP1_DX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ MCBSP1_DR, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ MCBSP1_CLKS, MUXMODE0, PULLTYPESELECT, INPUT },
|
||||
{ MCBSP1_FSX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ MCBSP1_CLKX, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ UART3_CTS_RCTX,MUXMODE0, PULLUDENABLE, INPUT },
|
||||
{ UART3_RTS_SD, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ UART3_RX_IRRX, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ UART3_TX_IRTX, MUXMODE0, PULLTYPENOSELECT, OUTPUT },
|
||||
{ HSUSB0_CLK, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_STP, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
|
||||
{ HSUSB0_DIR, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_NXT, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_DATA0, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_DATA1, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_DATA2, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_DATA3, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_DATA4, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_DATA5, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_DATA6, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ HSUSB0_DATA7, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ I2C1_SCL, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ I2C1_SDA, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ I2C2_SCL, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ I2C2_SDA, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ I2C3_SCL, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ I2C3_SDA, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ HDQ_SIO, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
|
||||
{ MCSPI1_CLK, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MCSPI1_SIMO, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ MCSPI1_SOMI, MUXMODE0, PULLTYPENOSELECT, INPUT },
|
||||
{ MCSPI1_CS0, MUXMODE0, PULLUDENABLE, INPUT },
|
||||
{ MCSPI1_CS1, MUXMODE0, PULLUDENABLE, OUTPUT },
|
||||
{ MCSPI1_CS2, MUXMODE4, PULLTYPENOSELECT, OUTPUT },
|
||||
{ MCSPI1_CS3, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ MCSPI2_CLK, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ MCSPI2_SIMO, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ MCSPI2_SOMI, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ MCSPI2_CS0, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ MCSPI2_CS1, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ SYS_NIRQ, MUXMODE0, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ SYS_CLKOUT2, MUXMODE4, (PULLTYPESELECT | PULLUDENABLE), INPUT },
|
||||
{ ETK_CLK, MUXMODE3, (PULLTYPESELECT | PULLUDENABLE), OUTPUT },
|
||||
{ ETK_CTL, MUXMODE3, PULLTYPESELECT, OUTPUT },
|
||||
{ ETK_D0, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D1, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D2, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D3, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D4, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D5, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D6, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D7, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D8, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D9, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D10, MUXMODE3, PULLTYPESELECT, OUTPUT },
|
||||
{ ETK_D11, MUXMODE3, PULLTYPESELECT, OUTPUT },
|
||||
{ ETK_D12, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D13, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D14, MUXMODE3, PULLTYPESELECT, INPUT },
|
||||
{ ETK_D15, MUXMODE3, PULLTYPESELECT, INPUT }
|
||||
{ SDRC_D0, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D1, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D2, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D3, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D4, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D5, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D6, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D7, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D8, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D9, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D10, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D11, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D12, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D13, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D14, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D15, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D16, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D17, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D18, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D19, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D20, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D21, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D22, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D23, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D24, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D25, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D26, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D27, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D28, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D29, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D30, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_D31, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_CLK, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_DQS0, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_CKE0, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ SDRC_CKE1, MUXMODE7, PULL_DISABLED, INPUT },
|
||||
{ SDRC_DQS1, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_DQS2, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ SDRC_DQS3, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_A1, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_A2, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_A3, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_A4, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_A5, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_A6, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_A7, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_A8, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_A9, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_A10, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_D0, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D1, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D2, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D3, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D4, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D5, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D6, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D7, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D8, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D9, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D10, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D11, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D12, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D13, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D14, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_D15, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_NCS0, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_NCS1, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
|
||||
{ GPMC_NCS2, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
|
||||
{ GPMC_NCS3, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
|
||||
{ GPMC_NCS4, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
|
||||
{ GPMC_NCS5, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_NCS6, MUXMODE1, PULL_DISABLED, INPUT },
|
||||
{ GPMC_NCS7, MUXMODE1, PULL_UP_SELECTED, INPUT },
|
||||
{ GPMC_CLK, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_NADV_ALE, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_NOE, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_NWE, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_NBE0_CLE, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ GPMC_NBE1, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_NWP, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ GPMC_WAIT0, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ GPMC_WAIT1, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ GPMC_WAIT2, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ GPMC_WAIT3, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ DSS_PCLK, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_HSYNC, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_PSYNC, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_ACBIAS, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA0, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA1, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA2, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA3, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA4, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA5, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA6, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA7, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA8, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA9, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA10, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA11, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA12, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA13, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA14, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA15, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA16, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA17, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA18, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA19, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA20, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA21, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA22, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ DSS_DATA23, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ CAM_HS, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ CAM_VS, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ CAM_XCLKA, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ CAM_PCLK, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ CAM_FLD, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ CAM_D0, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D1, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D2, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D3, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D4, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D5, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D6, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D7, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D8, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D9, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D10, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_D11, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CAM_XCLKB, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ CAM_WEN, MUXMODE4, PULL_DISABLED, INPUT },
|
||||
{ CAM_STROBE, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ CSI2_DX0, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CSI2_DY0, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CSI2_DX1, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ CSI2_DY1, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ MCBSP2_FSX, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ MCBSP2_CLKX, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ MCBSP2_DR, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ MCBSP2_DX, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ MMC1_CLK, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
|
||||
{ MMC1_CMD, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC1_DAT0, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC1_DAT1, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC1_DAT2, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC1_DAT3, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC1_DAT4, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC1_DAT5, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC1_DAT6, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC1_DAT7, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_CLK, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_CMD, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_DAT0, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_DAT1, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_DAT2, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_DAT3, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_DAT4, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_DAT5, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_DAT6, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MMC2_DAT7, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MCBSP3_DX, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ MCBSP3_DR, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ MCBSP3_CLKX, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ MCBSP3_FSX, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ UART2_CTS, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ UART2_RTS, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ UART2_TX, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ UART2_RX, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ UART1_TX, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ UART1_RTS, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ UART1_CTS, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ UART1_RX, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ MCBSP4_CLKX, MUXMODE1, PULL_DISABLED, INPUT },
|
||||
{ MCBSP4_DR, MUXMODE1, PULL_DISABLED, INPUT },
|
||||
{ MCBSP4_DX, MUXMODE1, PULL_DISABLED, INPUT },
|
||||
{ MCBSP4_FSX, MUXMODE1, PULL_DISABLED, INPUT },
|
||||
{ MCBSP1_CLKR, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ MCBSP1_FSR, MUXMODE4, PULL_UP_SELECTED, OUTPUT },
|
||||
{ MCBSP1_DX, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ MCBSP1_DR, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ MCBSP1_CLKS, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MCBSP1_FSX, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ MCBSP1_CLKX, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ UART3_CTS_RCTX,MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ UART3_RTS_SD, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ UART3_RX_IRRX, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ UART3_TX_IRTX, MUXMODE0, PULL_DISABLED, OUTPUT },
|
||||
{ HSUSB0_CLK, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_STP, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
|
||||
{ HSUSB0_DIR, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_NXT, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_DATA0, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_DATA1, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_DATA2, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_DATA3, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_DATA4, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_DATA5, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_DATA6, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ HSUSB0_DATA7, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ I2C1_SCL, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ I2C1_SDA, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ I2C2_SCL, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ I2C2_SDA, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ I2C3_SCL, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ I2C3_SDA, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ HDQ_SIO, MUXMODE4, PULL_UP_SELECTED, OUTPUT },
|
||||
{ MCSPI1_CLK, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MCSPI1_SIMO, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ MCSPI1_SOMI, MUXMODE0, PULL_DISABLED, INPUT },
|
||||
{ MCSPI1_CS0, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ MCSPI1_CS1, MUXMODE0, PULL_UP_SELECTED, OUTPUT },
|
||||
{ MCSPI1_CS2, MUXMODE4, PULL_DISABLED, OUTPUT },
|
||||
{ MCSPI1_CS3, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ MCSPI2_CLK, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ MCSPI2_SIMO, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ MCSPI2_SOMI, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ MCSPI2_CS0, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ MCSPI2_CS1, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ SYS_NIRQ, MUXMODE0, PULL_UP_SELECTED, INPUT },
|
||||
{ SYS_CLKOUT2, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_CLK, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
|
||||
{ ETK_CTL, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
|
||||
{ ETK_D0, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D1, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D2, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D3, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D4, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D5, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D6, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D7, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D8, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D9, MUXMODE4, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D10, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
|
||||
{ ETK_D11, MUXMODE3, PULL_UP_SELECTED, OUTPUT },
|
||||
{ ETK_D12, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D13, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D14, MUXMODE3, PULL_UP_SELECTED, INPUT },
|
||||
{ ETK_D15, MUXMODE3, PULL_UP_SELECTED, INPUT }
|
||||
};
|
||||
|
||||
VOID
|
||||
|
|
|
@ -280,10 +280,9 @@
|
|||
#define WAKEUP_OFFSET 14
|
||||
#define WAKEUP_MASK (0x2UL << WAKEUP_OFFSET)
|
||||
|
||||
#define PULLUDDISABLE (0x0UL << 0)
|
||||
#define PULLUDENABLE BIT0
|
||||
#define PULLTYPENOSELECT (0x0UL << 1)
|
||||
#define PULLTYPESELECT BIT1
|
||||
#define PULL_DOWN_SELECTED ((0x0UL << 1) | BIT0)
|
||||
#define PULL_UP_SELECTED (BIT1 | BIT0)
|
||||
#define PULL_DISABLED (0x0UL << 0)
|
||||
|
||||
#define OUTPUT (0x0UL) //Pin is configured in output only mode.
|
||||
#define INPUT (0x1UL) //Pin is configured in bi-directional mode.
|
||||
|
|
|
@ -36,6 +36,13 @@
|
|||
#define VSEL_3_00V 0x2
|
||||
#define VSEL_3_15V 0x3
|
||||
|
||||
#define TPS65950_GPIO_CTRL 0xaa //I2C_ADDR_GRP_ID2
|
||||
#define CARD_DETECT_ENABLE (BIT2 | BIT0) // GPIO ON + GPIO CD1 enabled
|
||||
|
||||
|
||||
#define GPIODATAIN1 0x98 //I2C_ADDR_GRP_ID2
|
||||
#define CARD_DETECT_BIT BIT0
|
||||
|
||||
//LEDEN register
|
||||
#define LEDEN 0xEE
|
||||
#define LEDAON BIT0
|
||||
|
|
File diff suppressed because it is too large
Load Diff
|
@ -21,16 +21,16 @@
|
|||
#include <Library/IoLib.h>
|
||||
#include <Library/PcdLib.h>
|
||||
#include <Library/UefiBootServicesTableLib.h>
|
||||
#include <Library/BaseMemoryLib.h>
|
||||
|
||||
#include <Protocol/EmbeddedExternalDevice.h>
|
||||
#include <Protocol/BlockIo.h>
|
||||
#include <Protocol/Cpu.h>
|
||||
#include <Protocol/DevicePath.h>
|
||||
|
||||
#include <Omap3530/Omap3530.h>
|
||||
#include <TPS65950.h>
|
||||
|
||||
#define MAX_RETRY_COUNT 100
|
||||
#define MAX_RETRY_COUNT (100*5)
|
||||
|
||||
#define HCS BIT30 //Host capacity support/1 = Supporting high capacity
|
||||
#define CCS BIT30 //Card capacity status/1 = High capacity card
|
||||
|
@ -59,18 +59,21 @@ typedef struct {
|
|||
typedef struct {
|
||||
UINT8 NOT_USED: 1; // Not used, always 1 [0:0]
|
||||
UINT8 CRC: 7; // CRC [7:1]
|
||||
|
||||
UINT8 RESERVED_1: 2; // Reserved [9:8]
|
||||
UINT8 FILE_FORMAT: 2; // File format [11:10]
|
||||
UINT8 TMP_WRITE_PROTECT: 1; // Temporary write protection [12:12]
|
||||
UINT8 PERM_WRITE_PROTECT: 1; // Permanent write protection [13:13]
|
||||
UINT8 COPY: 1; // Copy flag (OTP) [14:14]
|
||||
UINT8 FILE_FORMAT_GRP: 1; // File format group [15:15]
|
||||
|
||||
UINT16 RESERVED_2: 5; // Reserved [20:16]
|
||||
UINT16 WRITE_BL_PARTIAL: 1; // Partial blocks for write allowed [21:21]
|
||||
UINT16 WRITE_BL_LEN: 4; // Max. write data block length [25:22]
|
||||
UINT16 R2W_FACTOR: 3; // Write speed factor [28:26]
|
||||
UINT16 RESERVED_3: 2; // Reserved [30:29]
|
||||
UINT16 WP_GRP_ENABLE: 1; // Write protect group enable [31:31]
|
||||
|
||||
UINT32 WP_GRP_SIZE: 7; // Write protect group size [38:32]
|
||||
UINT32 SECTOR_SIZE: 7; // Erase sector size [45:39]
|
||||
UINT32 ERASE_BLK_EN: 1; // Erase single block enable [46:46]
|
||||
|
@ -79,8 +82,9 @@ typedef struct {
|
|||
UINT32 VDD_W_CURR_MIN: 3; // Max. write current @ VDD min [55:53]
|
||||
UINT32 VDD_R_CURR_MAX: 3; // Max. read current @ VDD max [58:56]
|
||||
UINT32 VDD_R_CURR_MIN: 3; // Max. read current @ VDD min [61:59]
|
||||
UINT32 C_SIZELow2: 2; // Device size [73:62]
|
||||
UINT32 C_SIZEHigh10: 10;// Device size [73:62]
|
||||
UINT32 C_SIZELow2: 2; // Device size [63:62]
|
||||
|
||||
UINT32 C_SIZEHigh10: 10;// Device size [73:64]
|
||||
UINT32 RESERVED_4: 2; // Reserved [75:74]
|
||||
UINT32 DSR_IMP: 1; // DSR implemented [76:76]
|
||||
UINT32 READ_BLK_MISALIGN: 1; // Read block misalignment [77:77]
|
||||
|
@ -88,9 +92,11 @@ typedef struct {
|
|||
UINT32 READ_BL_PARTIAL: 1; // Partial blocks for read allowed [79:79]
|
||||
UINT32 READ_BL_LEN: 4; // Max. read data block length [83:80]
|
||||
UINT32 CCC: 12;// Card command classes [95:84]
|
||||
|
||||
UINT8 TRAN_SPEED ; // Max. bus clock frequency [103:96]
|
||||
UINT8 NSAC ; // Data read access-time 2 in CLK cycles (NSAC*100) [111:104]
|
||||
UINT8 TAAC ; // Data read access-time 1 [119:112]
|
||||
|
||||
UINT8 RESERVED_5: 6; // Reserved [125:120]
|
||||
UINT8 CSD_STRUCTURE: 2; // CSD structure [127:126]
|
||||
}CSD;
|
||||
|
@ -143,8 +149,7 @@ typedef enum {
|
|||
WRITE
|
||||
} OPERATION_TYPE;
|
||||
|
||||
typedef struct
|
||||
{
|
||||
typedef struct {
|
||||
UINT16 RCA;
|
||||
UINTN BlockSize;
|
||||
UINTN NumBlocks;
|
||||
|
@ -155,4 +160,11 @@ typedef struct
|
|||
CSD CSDData;
|
||||
} CARD_INFO;
|
||||
|
||||
EFI_STATUS
|
||||
DetectCard (
|
||||
VOID
|
||||
);
|
||||
|
||||
extern EFI_BLOCK_IO_PROTOCOL gBlockIo;
|
||||
|
||||
#endif
|
||||
|
|
Loading…
Reference in New Issue