mirror of https://github.com/acidanthera/audk.git
UefiCpuPkg/PiSmmCpuDxeSmm: eliminate conditional jump in IA32 SmmStartup()
SMM emulation under both KVM and QEMU (TCG) crashes the guest when the
"jz" branch, added in commit d4d87596c1
("UefiCpuPkg/PiSmmCpuDxeSmm:
Enable NXE if it's supported", 2018-01-18), is taken.
Rework the propagation of CPUID.80000001H:EDX.NX [bit 20] to IA32_EFER.NXE
[bit 11] so that no code is executed conditionally.
Cc: Eric Dong <eric.dong@intel.com>
Cc: Jian J Wang <jian.j.wang@intel.com>
Cc: Jiewen Yao <jiewen.yao@intel.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: Ruiyu Ni <ruiyu.ni@intel.com>
Ref: http://mid.mail-archive.com/d6fff558-6c4f-9ca6-74a7-e7cd9d007276@redhat.com
Contributed-under: TianoCore Contribution Agreement 1.1
Signed-off-by: Laszlo Ersek <lersek@redhat.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
[lersek@redhat.com: XD -> NX code comment updates from Ray]
Reviewed-by: Ruiyu Ni <ruiyu.ni@intel.com>
[lersek@redhat.com: mark QEMU/TCG as well in the commit message]
This commit is contained in:
parent
e75ee97224
commit
8d4d55b15b
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@ -47,6 +47,8 @@ ASM_PFX(SmmStartup):
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mov eax, 0x80000001 ; read capability
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mov eax, 0x80000001 ; read capability
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cpuid
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cpuid
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mov ebx, edx ; rdmsr will change edx. keep it in ebx.
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mov ebx, edx ; rdmsr will change edx. keep it in ebx.
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and ebx, BIT20 ; extract NX capability bit
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shr ebx, 9 ; shift bit to IA32_EFER.NXE[BIT11] position
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DB 0x66, 0xb8 ; mov eax, imm32
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DB 0x66, 0xb8 ; mov eax, imm32
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ASM_PFX(gSmmCr3): DD 0
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ASM_PFX(gSmmCr3): DD 0
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mov cr3, eax
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mov cr3, eax
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@ -56,11 +58,8 @@ ASM_PFX(gSmmCr4): DD 0
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mov cr4, eax
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mov cr4, eax
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mov ecx, 0xc0000080 ; IA32_EFER MSR
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mov ecx, 0xc0000080 ; IA32_EFER MSR
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rdmsr
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rdmsr
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test ebx, BIT20 ; check NXE capability
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or eax, ebx ; set NXE bit if NX is available
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jz .1
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or ah, BIT3 ; set NXE bit
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wrmsr
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wrmsr
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.1:
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DB 0x66, 0xb8 ; mov eax, imm32
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DB 0x66, 0xb8 ; mov eax, imm32
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ASM_PFX(gSmmCr0): DD 0
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ASM_PFX(gSmmCr0): DD 0
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mov di, PROTECT_MODE_DS
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mov di, PROTECT_MODE_DS
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